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Wired or and and Circuits for CVS and CMOS Logic

IP.com Disclosure Number: IPCOM000044079D
Original Publication Date: 1984-Nov-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Griffin, WR: AUTHOR [+4]

Abstract

This article describes wired OR and AND circuits for buffered CMOS and CVS (cascode voltage switch) circuits with the devices in the buffer inverters rewired to provide two-way or wider AND and OR functions with no additional devices. Unlike the conventional approach to providing the ORing of the outputs of the logic blocks by going through an OR gate, this design provides the OR function by rewiring devices P1, N1, P2 and N2, as shown in Fig. 1. Thus, no additional devices are required. The wired OR is achieved without an additional stage delay. Logic Functions F and G are still available by inverting F and G. Rewired buffer devices can also be used to provide two-way or wider wired AND circuits, as shown in Fig. 2.

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Wired or and and Circuits for CVS and CMOS Logic

This article describes wired OR and AND circuits for buffered CMOS and CVS (cascode voltage switch) circuits with the devices in the buffer inverters rewired to provide two-way or wider AND and OR functions with no additional devices. Unlike the conventional approach to providing the ORing of the outputs of the logic blocks by going through an OR gate, this design provides the OR function by rewiring devices P1, N1, P2 and N2, as shown in Fig. 1. Thus, no additional devices are required. The wired OR is achieved without an additional stage delay. Logic Functions F and G are still available by inverting F and G. Rewired buffer devices can also be used to provide two-way or wider wired AND circuits, as shown in Fig. 2. Wider than two-way wired OR and AND functions can be provided, as well as combinations of AND and OR functions. With this use of wired ORs and ANDs, a compression of logic is possible; thus, performance, area, and power improvements are obtained.

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