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Low Power CMOS Nor Decoder for Automatically Powering Down Unselected Decoders

IP.com Disclosure Number: IPCOM000044081D
Original Publication Date: 1984-Nov-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Lipa, RA: AUTHOR

Abstract

A simple complementary metal-oxide-semiconductor (CMOS) bit decoder dissipates power whenever the input to the p-channel device is low and one of the inputs to an n-channel device is high. This occurs whenever AX0 transitions to ground and AX1, AX2 or AX3 remains at VH, as in Fig. 1. All address lines AX0 through AX3 and their complements AX0 through AX3 are precharged high. After the address is clocked into the chip, the selected decoder has all inputs low. After observing the state table (Fig. 2) of the address lines AX0, AX0 through AX3, AX3 an automatically powering-down decoder evolves, as in Fig. 3. An additional transistor 11 uses address AX0 as the gate input of an n-channel transistor with drain tied to node 1 and source tied to ground. This device clamps node 1 low when AX0 remains high in an unselected decoder.

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Low Power CMOS Nor Decoder for Automatically Powering Down Unselected Decoders

A simple complementary metal-oxide-semiconductor (CMOS) bit decoder dissipates power whenever the input to the p-channel device is low and one of the inputs to an n-channel device is high. This occurs whenever AX0 transitions to ground and AX1, AX2 or AX3 remains at VH, as in Fig. 1. All address lines AX0 through AX3 and their complements AX0 through AX3 are precharged high. After the address is clocked into the chip, the selected decoder has all inputs low. After observing the state table (Fig. 2) of the address lines AX0, AX0 through AX3, AX3 an automatically powering-down decoder evolves, as in Fig. 3. An additional transistor 11 uses address AX0 as the gate input of an n-channel transistor with drain tied to node 1 and source tied to ground. This device clamps node 1 low when AX0 remains high in an unselected decoder. When AX0 discharges and one of the addresses AX1, AX2 or AX3 remains high, a DC path to ground exists in the simple decoder. In the automatically powered-down decoder, this path to ground is broken as one of the p-channel inputs AX1 through AX3 transitions low. Node 2 charges and transistor 12 shuts off. A precharge signal discharges node 2 before the addresses are valid (Fig. 4).

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