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Browse Prior Art Database

Selective Powering of Ripple ALU for Improved POWER PERFORMANCE

IP.com Disclosure Number: IPCOM000044087D
Original Publication Date: 1984-Nov-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Bechade, RA: AUTHOR

Abstract

The selective powering of the ripple arithmetic logic unit (ALU) for improved power performance reduces power dissipation by 40% in high performance applications, by varying the size of the load devices in otherwise identical bit slice sub-macros. This selective powering modifies the power level of some circuits for different bit positions and conserves geometric compatibility with all of the bit slice in the ALU. The input inverters, input phase inverters, function generator and output push-pull have all been designed with up to three different power levels, resulting in a 40% saving in power versus an all high power design at the same performance. When compared to an all low power design, it shows a 20% improvement in performance and a 7% improvement in power performance.

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Selective Powering of Ripple ALU for Improved POWER PERFORMANCE

The selective powering of the ripple arithmetic logic unit (ALU) for improved power performance reduces power dissipation by 40% in high performance applications, by varying the size of the load devices in otherwise identical bit slice sub-macros. This selective powering modifies the power level of some circuits for different bit positions and conserves geometric compatibility with all of the bit slice in the ALU. The input inverters, input phase inverters, function generator and output push-pull have all been designed with up to three different power levels, resulting in a 40% saving in power versus an all high power design at the same performance. When compared to an all low power design, it shows a 20% improvement in performance and a 7% improvement in power performance. ALU DESIGN POWER PERFORMANCE POWER PERFORMANCE All bit high power 264 mW 98.4 ns 25978 pj Selective powering 155 mW 98.4 ns 15252 pj All bit low power 133 mW 123 ns 16359 pj Fig. 1 shows a circuit diagram of the one-bit slice of the ALU, and Fig. 2 shows the delay versus bit positions.

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