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Browse Prior Art Database

Dual-Mode Address Relocate System

IP.com Disclosure Number: IPCOM000044096D
Original Publication Date: 1984-Nov-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

Kriz, TA: AUTHOR

Abstract

A data processing system is provided with single address relocate structure which efficiently operates in a zero-origin non-VM (virtual memory) relocate mode and a full VM mode. Facilities are included to support: 1) 4K byte fixed page size, 2) memory protection, 3) bypass of an address translate function, and 4) page access and write reference detection. With reference to the drawing, the relocate structure includes a fast random-access memory 10. The size of memory 10 is 4K by 4 bytes (8 bits per byte). Memory 10 functions as an address translation table having the fields shown in the drawing.

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Dual-Mode Address Relocate System

A data processing system is provided with single address relocate structure which efficiently operates in a zero-origin non-VM (virtual memory) relocate mode and a full VM mode. Facilities are included to support: 1) 4K byte fixed page size, 2) memory protection, 3) bypass of an address translate function, and 4) page access and write reference detection. With reference to the drawing, the relocate structure includes a fast random-access memory 10. The size of memory 10 is 4K by 4 bytes (8 bits per byte). Memory 10 functions as an address translation table having the fields shown in the drawing. Memory 10 is used to support a simple 24-bit logical to physical address translation in the non- VM mode and a 32-bit effective logical (byte referenced) address (8-bit segment or process ID plus 24-bit processor logical address) to a 24-bit physical address in the VM mode. The memory, hereafter table 10, is mapped (via address bits A1-A13) to a 16K-byte region of real memory to allow table read/write access under program control for purposes of table update and status checking. A processor 11 outputs logical address bits A1-A23. The processor may be a Motorola 68000 microprocessor for the non-VM mode or a 68010 microprocessor for the VM mode. Associated with processor 11 are function code bits FC0-2, a bus grant acknowledge signal BGACK, and data bits D0-15. Address bits 1-11 are fed to a register 14 to form physical address bits PA1-11. Bits A12-23 are fed to a multiplexer 15 and, in response to a BYPASS signal, form bits PA12-23. Table 12 is loaded with data from lines D0-15 through a bidirectional driver 16. Table 12 is loaded when the system is in supervisor mod...