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Browse Prior Art Database

Digital Automatic Gain Control Circuit

IP.com Disclosure Number: IPCOM000044100D
Original Publication Date: 1984-Nov-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Fukuta, M: AUTHOR

Abstract

This article describes a digital automatic gain control (AGC) circuit used in a CCD (charge-coupled device) image sense circuit, in which a gain is so controlled that a peak value of output voltage is regulated to a reference value. The circuit includes an analog/digital (A/D) converter which operates as a divider. Fig. 1 shows the concept of the digital AGC circuit. The CCD sensor 1 includes photodiode elements arranged in the direction of width of a document 2. The CCD sensor senses the image of the document in the direction of its width. As the CCD sensor array 1 moves relative to the document 2, the CCD sensor array 1 generates analog signals of successive scan lines. The analog signal is applied to the digital AGC circuit 5 through a pre-amplifier and a sample hold circuit 4.

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Digital Automatic Gain Control Circuit

This article describes a digital automatic gain control (AGC) circuit used in a CCD (charge-coupled device) image sense circuit, in which a gain is so controlled that a peak value of output voltage is regulated to a reference value. The circuit includes an analog/digital (A/D) converter which operates as a divider. Fig. 1 shows the concept of the digital AGC circuit. The CCD sensor 1 includes photodiode elements arranged in the direction of width of a document 2. The CCD sensor senses the image of the document in the direction of its width. As the CCD sensor array 1 moves relative to the document 2, the CCD sensor array 1 generates analog signals of successive scan lines. The analog signal is applied to the digital AGC circuit 5 through a pre-amplifier and a sample hold circuit 4. The digital AGC circuit 5 includes the A/D converter 6, a peak hold circuit 7, a comparator circuit 8 and an digital integrator 9. The A/D converter 6 operates as a divider in which the analog signal Vx is divided by a feedback control signal Va, which is generated as follows. At the start of the document scan, the peak hold circuit 7 and the integrator 9 are reset. The peak hold circuit 7 is also reset at the end of scan of each scan line. A desired peak value Vpeak is supplied to an input 8A of the comparator circuit 8; then, at the start of the document scan, the value in the integrator 9 is Vpeak. For each scan line, a peak value is detected an...