Browse Prior Art Database

J-K LSSD SRL for Use in a Self-Testable Logic Circuit

IP.com Disclosure Number: IPCOM000044104D
Original Publication Date: 1984-Nov-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Burbank, HC: AUTHOR [+4]

Abstract

A J-K LSSD SRL for use in a self-testable logic circuit allows the self-test feature to be implemented at the final component test point using existing test methodology or new form factors, using self-test to save time. This feature is implementable during in-field use. This latch can be used in both the linear feedback shift register (LFSR) mode and multiple input signature register (MISR) mode. When the test line is held low, the latch will perform as a normal level sensitive scan design (LSSD) latch. This particular configuration is unique since it will operate with a normal system clock cycle (C/B) in the self-test mode. Other configurations require additional clocks (A/B) which limit their use in system/field tests.

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J-K LSSD SRL for Use in a Self-Testable Logic Circuit

A J-K LSSD SRL for use in a self-testable logic circuit allows the self-test feature to be implemented at the final component test point using existing test methodology or new form factors, using self-test to save time. This feature is implementable during in-field use. This latch can be used in both the linear feedback shift register (LFSR) mode and multiple input signature register (MISR) mode. When the test line is held low, the latch will perform as a normal level sensitive scan design (LSSD) latch. This particular configuration is unique since it will operate with a normal system clock cycle (C/B) in the self-test mode. Other configurations require additional clocks (A/B) which limit their use in system/field tests. The self-test methodology is based on random patterns being generated by an LFSR and applied to combinatorial logic for testing. The use of random patterns requires all latches to have determinate states. The set-reset latch could not be used since S=1, R=1 results in an undetermined state. The J-K design eliminates the indeterminate state and still allows the design flexibility of an S-R latch. This circuit operates as follows: 1. Test = 0; C/B Clock Cycle T Normal System Operation 2. Test = 0; A/B Clock Cycle T Normal LSSD Operation 3. Test = 1; C/B Clock Cycle T Self-Test Operation (MISR) 4. Test = 1; A/B Clock Cycle T Self-Test (LFSR use only)

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