Browse Prior Art Database

Total Panel Soldering

IP.com Disclosure Number: IPCOM000044114D
Original Publication Date: 1984-Nov-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Bora, MY: AUTHOR

Abstract

There is shown and described a process for soldering full panels during circuit panel manufacturing. This technique assembles various sized cards with surface-mounted components in panel form from placement to solder reflow operations, significantly reducing unit hours, and improving yield and reliability. The figure shows the process flow. The technique requires surface-mounted components provided with suitable connector surfaces, such as pins with solder, tin, or gold plating, and a carrier provided with surface circuit lines. After the protective coating operation, solder paste is screened to the carrier, card or substrate, in full panel form. This technique reduces handling time, handling defects, number of masks and screens used, waste of solder paste, and wear and tear on screening equipment.

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Total Panel Soldering

There is shown and described a process for soldering full panels during circuit panel manufacturing. This technique assembles various sized cards with surface- mounted components in panel form from placement to solder reflow operations, significantly reducing unit hours, and improving yield and reliability. The figure shows the process flow. The technique requires surface-mounted components provided with suitable connector surfaces, such as pins with solder, tin, or gold plating, and a carrier provided with surface circuit lines. After the protective coating operation, solder paste is screened to the carrier, card or substrate, in full panel form. This technique reduces handling time, handling defects, number of masks and screens used, waste of solder paste, and wear and tear on screening equipment. When components are placed on the carrier in full panel form, set-up time is reduced as are handling defects in loading and unloading. Unit placement time is also reduced since the placement head can place identical components on the panel with fewer movements. A carrier in full panel form is more rigid during the placement operation. The carrier can also be processed through reflow operation for joining in full panel form, thus reducing unit hours, set-up time, and handling defects. Moreover, since the carrier can be cleaned in full panel form, set-up time, unit hours, handling defects, and waste cleaning agent associated with this step are redu...