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Interrupt Vector Generation Through Priority Generations

IP.com Disclosure Number: IPCOM000044121D
Original Publication Date: 1984-Nov-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Hayes, EN: AUTHOR [+2]

Abstract

The article describes an apparatus and method for generating interrupt vectors in a microprocessor-based system. A negative active vector enable line is ORed with a plurality of prioritized lines to produce the actual bits of the interrupt vectors. Each prioritized line represents an interrupt level. Since only one priority line is active at a particular time, the vector consists of eight bits all having the same value or state excepting the vector bit corresponding to the active priority line. In the figure, the interrupt lines from external devices are fed over multiplexer bus 10 into the prioritization circuit which generates a plurality of priority lines 0-7.

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Interrupt Vector Generation Through Priority Generations

The article describes an apparatus and method for generating interrupt vectors in a microprocessor-based system. A negative active vector enable line is ORed with a plurality of prioritized lines to produce the actual bits of the interrupt vectors. Each prioritized line represents an interrupt level. Since only one priority line is active at a particular time, the vector consists of eight bits all having the same value or state excepting the vector bit corresponding to the active priority line. In the figure, the interrupt lines from external devices are fed over multiplexer bus 10 into the prioritization circuit which generates a plurality of priority lines 0-7. The prioritization circuit processes an incoming interrupt signal so that only one interrupt (0-7) to the microprocessor (not shown) occurs at a given time and that the interrupt that is being serviced is of the highest degree of importance (or priority) of those interrupts that are active (or need servicing). A negative active vector enable signal is ORed with each priority line to produce the actual bits of the interrupt vector. Thus, a single interrupt vector is supplied by the microprocessor on the data bus. All the bits excepting the one representing the active interrupt are in the same state. For example, if the active state of the priority signal is one, and the vector is to indicate that I6 (interrupt 6) should be serviced, then the vector...