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Hierarchical Level Sensitive Scan Design Rules Checking

IP.com Disclosure Number: IPCOM000044124D
Original Publication Date: 1984-Nov-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 3 page(s) / 36K

Publishing Venue

IBM

Related People

Goel, P: AUTHOR [+2]

Abstract

A method is described for early checking, via a hierarchical approach, that a logic structure complies with the primary rules for Level Sensitive Scan Design (LSSD). It assumes that the logic has a hierarchical structure (e.g., chips act as "vassals" of a "lord" chip carrier package). It also assumes that at the lowest vassal level (e.g., chip-level), the LSSD rules are checked by a full structure method, and that the inter-vassal logic contains no function other than implicit dotting. This hierarchical method can then be used to check the LSSD rules at higher package levels (e.g., module, board, machine) without requiring access to the full structure at each of those levels. LSSD makes automatic test pattern generation practical for large logic structures. It is described in: E. B. Eichelberger and T. W.

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Hierarchical Level Sensitive Scan Design Rules Checking

A method is described for early checking, via a hierarchical approach, that a logic structure complies with the primary rules for Level Sensitive Scan Design (LSSD). It assumes that the logic has a hierarchical structure (e.g., chips act as "vassals" of a "lord" chip carrier package). It also assumes that at the lowest vassal level (e.g., chip-level), the LSSD rules are checked by a full structure method, and that the inter-vassal logic contains no function other than implicit dotting. This hierarchical method can then be used to check the LSSD rules at higher package levels (e.g., module, board, machine) without requiring access to the full structure at each of those levels. LSSD makes automatic test pattern generation practical for large logic structures. It is described in: E. B. Eichelberger and T. W. Williams, "A Logic Design structure for LSI Testability," Proc. 14th Design Automation Conference, June 1977, pp. 462-468. A full structure LSSD rules checking program is described in: H. C. Godoy, G. B. Franklin and P. S. Bottorff, "Automatic Checking of Logic Design Structures for Compliance with Testability Ground Rules," Proc. 14th Design Automation Conference, June 1977, pp. 469-478. Such a method requires that an entire model that describes the logic design (i.e., full structure) be loaded into addressable storage. It is, therefore, storage limited. This limit can be extended by paging data into and out of addressable storage, but paging results in reduced performance. This hierarchical method is not storage limited, and its performance for large structures is projected to be better than that of a full structure method. Although it does not have the extendibility of a full structure method for checking most of the LSSD rules, this hierarchical method can be used to check the same primary rules that are currently checked by the full structure method. Referring to the figure, a package 1 contains a number of interconnected chips 2 and package pins 3. The package represents a "lord" level and a chip represents a "vassal". At each "lord" level the hierarchial method requires two steps: 1) Abstract LSSD-related information for each vassal and associate that information in terms of the vassal's input and output pins. 2) Treat each vassal as a "black blox" and use the inter-vassal connectivity information and abstracted vassal pin information to check the rules for the lord. The rules and method for checking are as follows: Rule A.1 - No loops can exist outside the Shift Register Latches (SRLs) in a chip. Vassal level: Create an m by n array, where m is the number of the vassal's inputs and n is the number of the vassal's outputs. Set each (m,n) element to 1 if a combinational path exists between the corresponding vassal input and vassal output. Otherwise, set the element to 0. Lord level: Use the m by n array for each vassal combined with the inter-vassal connectivity to det...