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Densely Arrayed EEPROM Having Low-Voltage Tunnel Write

IP.com Disclosure Number: IPCOM000044125D
Original Publication Date: 1984-Nov-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 5 page(s) / 61K

Publishing Venue

IBM

Related People

Adler, E: AUTHOR

Abstract

A combination of semiconductor device fabrication techniques is employed to construct an electrically erasable and programmable read-only memory (EEPROM) in which the memory cells are polysilicon floating-gate MOSFETs arranged serially in blocks of AND-type circuitry. The oxide insulation on the floating gates can be readily tunneled by low write voltage to charge these gates for bit storage. Groups of serially connected memory cells form AND circuits in word blocks that require relatively few points of electrical contact between the cells and the drive lines. This arrangement permits dense positioning of the memory cells and low-power operation of the array. Fig. 1 shows on a simplified scale the general format of the EEPROM circuitry.

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Densely Arrayed EEPROM Having Low-Voltage Tunnel Write

A combination of semiconductor device fabrication techniques is employed to construct an electrically erasable and programmable read-only memory (EEPROM) in which the memory cells are polysilicon floating-gate MOSFETs arranged serially in blocks of AND-type circuitry. The oxide insulation on the floating gates can be readily tunneled by low write voltage to charge these gates for bit storage. Groups of serially connected memory cells form AND circuits in word blocks that require relatively few points of electrical contact between the cells and the drive lines. This arrangement permits dense positioning of the memory cells and low-power operation of the array.

Fig. 1 shows on a simplified scale the general format of the EEPROM circuitry. A group of four word lines W0 to W3 is arranged repetitively in different word blocks such as WB0 and WB1, each of which is controlled by a pair of complementary word block switch lines, such as WBS1 and WBS1 in the case of word block WB1. Associated with each of the bit lines such as B0 and B1, in each of the word blocks such as WB0 and WB1, is a group of n-channel MOSFETs whose source and drain terminals are connected in series to provide a type of AND-gate circuitry. Each of the AND circuit groups includes four memory cells of the floating gate type, associated respectively with the word lines W0 to W3 of the respective word block, and two additional FETs which serve as decode selection devices associated respectively with the word block switch lines. One of these decode selection devices may be turned on to connect the drain and source terminals of its AND-gate series to a bit line; the other may be turned on to connect these terminals to a source of reference potential QGND. The functions of these switches during write and read operations will be explained presently. Fig. 2 is a sectional view of a floating gate memory cell taken along its word line. A diffused n-channel in the substrate is covered by a layer 1 of silicon oxide, upon which a polysilicon floating gate 4 is positioned. Gate 4 is covered by a layer 2 of polysilicon oxide upon which a polysilicon word line 3 is deposited. The word line, in effect, is a second gate. The oxide layer 1 can be made very thin.

The polysilicon oxide layer 2 will support tunneling action at less than half the field of oxide grown on single-crystal silicon. The tunneling property can be enhanced further by special processing techniques such as roughening the polysilicon gate 4 and doping the polysilicon oxide layer 2 with silicon, thereby reducing the write voltage requirement still further. Fig. 3 is a top view of the memory cell, omitting insulation. The n+ source and drain diffusions are made after definition of the polysilicon floating gate to ease overlap requirements between the polysilicon layers, as indicated in the sectional view, Fig. 4. In describing how digital information is written into...