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Delay INTEGRATOR

IP.com Disclosure Number: IPCOM000044127D
Original Publication Date: 1984-Nov-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 3 page(s) / 57K

Publishing Venue

IBM

Related People

Boyd, JB: AUTHOR [+3]

Abstract

The delay integrator is used in a phase-locked loop for recovering coded data. The delay integrator generates data-late information. For good phase-locked-loop operation, the data-late information must be reasonably accurate and have a small deadband. This delay integrator design features turn-on and turn-off enhancements as well as a combined clamp and comparator function. Basic delay integrator operation is depicted in the timing diagram of Fig. 1. The delay integrator is shown in Fig. 2. To understand the combined clamp and comparator function, reference is now made to Fig. 2. For basic operation: Short R5, R6, R8, R9, and Rs. Return R1 to Vcc instead of the emitter of Q5. Remove R7, CR9, Q5, Q6, Q7, Q8, and I3. Assume I1 = 2I2.

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Delay INTEGRATOR

The delay integrator is used in a phase-locked loop for recovering coded data. The delay integrator generates data-late information. For good phase-locked- loop operation, the data-late information must be reasonably accurate and have a small deadband. This delay integrator design features turn-on and turn-off enhancements as well as a combined clamp and comparator function. Basic delay integrator operation is depicted in the timing diagram of Fig. 1. The delay integrator is shown in Fig. 2. To understand the combined clamp and comparator function, reference is now made to Fig. 2. For basic operation: Short R5, R6, R8, R9, and Rs. Return R1 to Vcc instead of the emitter of Q5. Remove R7, CR9, Q5, Q6, Q7, Q8, and I3. Assume I1 = 2I2. Then, with "+ INTEGRATE" high, Q1 will conduct current I1 and I2 will flow into timing capacitor CT. Capacitor voltage, Vc, will rise, causing the Q3 emitter-base to turn off, thus turning Q4 on bringing the "+ INTEGRATOR DISCHARGED" output low. With the signal "+ INTEGRATE" low, Q2 conducts I1, resulting in a net current I2 - I1 = I2 - 2I2 = -I2 out of the capacitor. The capacitor voltage, Vc, will decrease until the Q3 emitter-base is forward biased which will then clamp Vc and turn Q4 off, resulting in "+ INTEGRATOR DISCHARGED" high. Thus, Q3 serves a double purpose: clamp and comparator. With the scheme just described, an objectionable deadband can exist due to the small difference between the final clamp level and the comparator sensitivity. One approach to solving this problem is to add a series resistor, Rs (Fig. 2). The effect of Rs is shown in Fig. 3B, which should be compared with Fig. 3A. Though the use of speed-up resistor Rs may be suitable for some applications, it may be seen from Fig. 3B that a pulse-width distortion (shrinkage) occurs. A turn-on enhancement without Rs may be implemented with additional circuitry indicated by a "+" in Fig. 2 (Rs = 0). The comparator threshold is varied by the "+ INTEGRATE" command, as indicated in Fig. 4. This scheme produces less pulse-width distortion than the addition of Rs. When "+ INTEGRATE" is high, Q1 conducts I1, causing a voltage drop across R5 which is translated by emitter follower Q5, thus turning Q3 off, resulting in Q4 turni...