Browse Prior Art Database

IBM Series/1 Channel Simulator

IP.com Disclosure Number: IPCOM000044131D
Original Publication Date: 1984-Nov-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 3 page(s) / 70K

Publishing Venue

IBM

Related People

Davis, GT: AUTHOR [+4]

Abstract

Signature analysis techniques for use in testing and troubleshooting electronic circuits have limitations where feedback situations are present. This article describes a technique for testing circuits in channel attachment cards by simulating the channel and utilizing the microprocessor on the card-under-test (c-u-t) to exercise the I/O portion of the c-u-t via the simulator. In that manner, the "handshaking" feedback protocols of the channel are simulated and problems of synchronizing the IBM Series/1 test equipment processor with the microprocessor on the c-u-t is eliminated. The circuit shown in the figure avoids the problems of testing a Series/1 channel attachment card by providing a channel simulator which is controlled by the card-under-test.

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IBM Series/1 Channel Simulator

Signature analysis techniques for use in testing and troubleshooting electronic circuits have limitations where feedback situations are present. This article describes a technique for testing circuits in channel attachment cards by simulating the channel and utilizing the microprocessor on the card-under-test (c- u-t) to exercise the I/O portion of the c-u-t via the simulator. In that manner, the "handshaking" feedback protocols of the channel are simulated and problems of synchronizing the IBM Series/1 test equipment processor with the microprocessor on the c-u-t is eliminated. The circuit shown in the figure avoids the problems of testing a Series/1 channel attachment card by providing a channel simulator which is controlled by the card-under-test. The microprocessor's address bus 20 interfaces directly to the simulator's address decode circuitry 17; eight adjacent I/O port addresses are made available in the microprocessor's I/O map. (Memory mapped I/O or multiplexed I/O ports with the same address would also be possible.) A separate chip select control line is generated for each of these decoded addresses. The microprocessor data bus 21 interfaces directly to a single bus buffer module 1 to eliminate excess loading on the main bus. The channel simulator's internal bus 18 is tied to six registers, each of which is loaded by a separate chip select control line from the decode circuit 17. Two of these registers are 8-bit latch circuits 14 and 15. These registers are loaded with address/command information for the most-significant byte (MSB) 14 and the least-significant byte (LSB) 15 of the Series/1 channel address bus. Two additional registers 11 and 13 are actually 9-bit first-in-first-out (FIFO) memories. These registers are loaded with data for the most-significant byte 11 and the least-significant byte 13 of the Series/1 channel data bus. A FIFO is used instead of a register, so that multiple cycle-steal operations can be implemented back-to-back, with different data bus contents for each cycle, and without requiring the microprocessor to update the registers between cycles. Eight of the nine bits in each FIFO 11 and 13 are loaded directly from the data bus. The ninth bit to each FIFO is generated by a parity generator circuit 12 to match the contents of the data bus 18 which is also being loaded into the FIFO 11 or 13. The fifth register is an 8-bit latch 10 which is segmented into two 4-bit sections, each with its own output control. The first 4-bits drive the cycle steal (C.S.) status lines of the Series/1 channel. The other four bits drive the poll ID lines of the Series/1 channel. The sixth register is also an 8-bit latch 2 which serves two functions. One group of outputs from this register is used to discretely drive miscellaneous control lines in the Series/1 channel and to select between odd and even parity on the par...