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Chip Design Enhancement for Reduced Power Dissipation in Chip-In-Place Test

IP.com Disclosure Number: IPCOM000044134D
Original Publication Date: 1984-Nov-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Banker, DC: AUTHOR [+4]

Abstract

In a packaging structure containing a number of interconnected integrated circuit chips it may be desirable to reduce the power supplied to at least certain chips which are not currently undergoing "test". Figs. 1-3 each show known circuits having a "standby input" for reducing chip power during test or standby status. Standby power is reduced to less than 10% of normal operating power by the special gating circuits. Off-chip driver and output inhibit circuits (not shown) remain operational to permit deselection (open circuiting) of dotted outputs. Individual circuits are turned off by a distributed reference voltage (not shown), allowing existing current sources to be used for power reduction in some logic circuits. Reference P. Goel and M. T.

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Chip Design Enhancement for Reduced Power Dissipation in Chip-In-Place Test

In a packaging structure containing a number of interconnected integrated circuit chips it may be desirable to reduce the power supplied to at least certain chips which are not currently undergoing "test". Figs. 1-3 each show known circuits having a "standby input" for reducing chip power during test or standby status. Standby power is reduced to less than 10% of normal operating power by the special gating circuits. Off-chip driver and output inhibit circuits (not shown) remain operational to permit deselection (open circuiting) of dotted outputs. Individual circuits are turned off by a distributed reference voltage (not shown), allowing existing current sources to be used for power reduction in some logic circuits. Reference P. Goel and M. T. McMahon, "Electronic Chip-In-Place Test" ACM IEEE, Nineteenth Design Automation Conference Proceedings (Caesars Palace, Las Vegas Nevada, June 14-16, 1982), IEEE Catalog No. 82CH1759-0, Paper No. 30.1, pages 482-488.

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