Browse Prior Art Database

Universal Electronic Package

IP.com Disclosure Number: IPCOM000044136D
Original Publication Date: 1984-Nov-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 78K

Publishing Venue

IBM

Related People

Goldmann, LS: AUTHOR

Abstract

This packaging concept allows flexibility in design, low cost and reparability. It involves mechanical stacking of thin ceramic sublayers and interconnection by thin copper "hat pins". This substrate 10 is made up of a plurality of layers 12, 14, 16 and 18. The layers can be made of (1) pressed ceramic with thin or thick film metallization on one side or both, (2) pressed ceramic with added metal-glass or polyimide metal layers, and (3) multilayer ceramic substrates, or any combination thereof. Semiconductor chips 20, discrete components 22 and/or wires may be bonded to the top or bottom of any layer. Alignment and mechanical support for the various layers are provided by a stacking mechanism remote from the active substrate area, such as protrusions 24 that fit into aligned depressions 26.

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Universal Electronic Package

This packaging concept allows flexibility in design, low cost and reparability. It involves mechanical stacking of thin ceramic sublayers and interconnection by thin copper "hat pins". This substrate 10 is made up of a plurality of layers 12, 14, 16 and 18. The layers can be made of (1) pressed ceramic with thin or thick film metallization on one side or both, (2) pressed ceramic with added metal-glass or polyimide metal layers, and (3) multilayer ceramic substrates, or any combination thereof. Semiconductor chips 20, discrete components 22 and/or wires may be bonded to the top or bottom of any layer. Alignment and mechanical support for the various layers are provided by a stacking mechanism remote from the active substrate area, such as protrusions 24 that fit into aligned depressions 26. Other alignment and mechanical support can be provided, such as bolting with suitable spacing means. Pins 28 or other suitable connections are provided on the bottom substrate to make connection with a card or board. Interconnections between the various layers are made by an array of thin copper rods 30 which have been coated with a low melt solder, such as 63 SnPb. Metallized areas on the various substrate surfaces define which surfaces are to be interconnected. As illustrated in Fig. 2, the copper rods 30 disposed in aligned holes 32 make contact with thin film metallurgy 34 on the top side of layer 12 and also with metallurgy 36 on the bottom si...