Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Two-Device CMOS Logic Functions

IP.com Disclosure Number: IPCOM000044142D
Original Publication Date: 1984-Nov-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Hiltebeitel, JA: AUTHOR

Abstract

A minimum of four devices, 2N and 2P, are generally required to realize the "NAND" and "NOR" functions in a complementary metal oxide semiconductor (CMOS) and an additional two devices (inverters) are required for the "AND" and "OR" functions. This article describes four simple two-device, two-input functions for use where area is at a premium, as might be found in custom very large-scale integration or in high density gate array designs. The four simple two-device, two-input functions, ab (Fig. 1), a b (Fig. 2), ab (Fig. 3) and a + b (Fig. 4), are shown accompanied by tables indicating two additional logic levels, 0 and 1, having the relationship 0 > 0 and 1 < 1. However, since 0 < Vug and 1 > Vug, where Vug is the unity-gain point, subsequent logic stages can be designed to resolve the levels correctly.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Two-Device CMOS Logic Functions

A minimum of four devices, 2N and 2P, are generally required to realize the "NAND" and "NOR" functions in a complementary metal oxide semiconductor (CMOS) and an additional two devices (inverters) are required for the "AND" and "OR" functions. This article describes four simple two-device, two-input functions for use where area is at a premium, as might be found in custom very large-scale integration or in high density gate array designs. The four simple two-device, two- input functions, ab (Fig. 1), a b (Fig. 2), ab (Fig. 3) and a + b (Fig. 4), are shown accompanied by tables indicating two additional logic levels, 0 and 1, having the relationship 0 > 0 and 1 < 1. However, since 0 < Vug and 1 > Vug, where Vug is the unity-gain point, subsequent logic stages can be designed to resolve the levels correctly. These circuits can be buffered with an inverter to restore full logic levels and provide fan-out.

1

Page 2 of 2

2

[This page contains 3 pictures or other non-text objects]