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Multiprocessor Configuration Switch Control

IP.com Disclosure Number: IPCOM000044158D
Original Publication Date: 1984-Nov-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Schaber, MO: AUTHOR [+2]

Abstract

In a multiprocessor (MP) system assembled from uniprocessors or dyadic processors, it is necessary to establish a control point which determines the configuration to be established for automatic power-on. Usually this configuration is controlled at one place, such as a control panel, which may or may not have to be tested every time the system is initialized. The drawing shows logic for controlling MP mode from more than one source providing flexibility for the total reconfiguration of a processor system. A processor controller uses the output of a single switch to stipulate isolation or to allow the processor controller microcode to configure the system to multiprocessor mode under the control of a single service processor.

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Multiprocessor Configuration Switch Control

In a multiprocessor (MP) system assembled from uniprocessors or dyadic processors, it is necessary to establish a control point which determines the configuration to be established for automatic power-on. Usually this configuration is controlled at one place, such as a control panel, which may or may not have to be tested every time the system is initialized. The drawing shows logic for controlling MP mode from more than one source providing flexibility for the total reconfiguration of a processor system. A processor controller uses the output of a single switch to stipulate isolation or to allow the processor controller microcode to configure the system to multiprocessor mode under the control of a single service processor. To establish multiple control points 1, the single switch bit must be expanded to additional hardware that will buffer the state of all the various switches (3 in this example) and detect a change in the state of the switches. The triggers 2 are power on reset to the state of the switches 1, and the MP status bit 3 is appropriately set. If any switch changes state after power-on, the buffer bits are compared to the switch bits and, if appropriate, the status bit is updated and the buffer is set to the new switch state. The status bit 3 would be unaffected if a switch which is statically different from the status bit is changed, but the reverse situation would affect the status bit. One switch 1 acts as the primary switch for power-on. This is the switch (SW
1) located at the primary control panel. The other switches are used for remoted configuration...