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Browse Prior Art Database

Method for Forming Laterally Graded Fet Junctions

IP.com Disclosure Number: IPCOM000044184D
Original Publication Date: 1984-Nov-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

El-Kareh, B: AUTHOR [+2]

Abstract

This article describes of method of fabricating shallow graded junctions with a highly doped region for the purpose of low sheet resistance and a lightly doped graded shallow extension toward the device channel (which determines the device properties). This extension can be made both shallow and lightly doped to reduce undesirable multiplication of leakage current to substrate and hot electron threshold voltage instability. The method of fabrication is as follows: 1. Use the conventional silicon gate process up through deposition and definition of the polysilicon gate 11, as shown in Fig. 1. Deposit a layer 12 of chemical vapor deposition (CVD) arsenic-doped oxide to a thickness of the desired junction extension (Fig. 2). 2.

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Method for Forming Laterally Graded Fet Junctions

This article describes of method of fabricating shallow graded junctions with a highly doped region for the purpose of low sheet resistance and a lightly doped graded shallow extension toward the device channel (which determines the device properties). This extension can be made both shallow and lightly doped to reduce undesirable multiplication of leakage current to substrate and hot electron threshold voltage instability. The method of fabrication is as follows: 1. Use the conventional silicon gate process up through deposition and definition of the polysilicon gate 11, as shown in Fig. 1. Deposit a layer 12 of chemical vapor deposition (CVD) arsenic-doped oxide to a thickness of the desired junction extension (Fig. 2). 2. Perform a directional dry etch of the arsenic-doped oxide 12 sufficient to remove the thickness of the doped oxide in planar regions. This will leave a doped oxide spacer 13 on the vertical side walls of polysilicon gate 11 (Fig. 3). 3. At this point, a conventional process sequence is resumed with an ion implantation to form n+ junctions 14 which are offset from the gated channel 11 by the width of the doped spacer oxide. During the drive-in sequence, the arsenic from the doped oxide is driven into the silicon to form a lightly n doped region 15 adjacent to the device channel at the same time that the n+ junctions 14 are formed by the diffusion of the implanted ions (Fig. 4). 4. An alternate...