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Buffered CMOS Masterslice Cell for Logic

IP.com Disclosure Number: IPCOM000044190D
Original Publication Date: 1984-Nov-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 63K

Publishing Venue

IBM

Related People

Piro, RA: AUTHOR [+2]

Abstract

This article describes a cell which allows the programmable use of either the conventional or buffered complementary metal oxide semiconductor (CMOS) circuit technique. This allows the speed of the conventional circuit, when driving small capacitive loads, and the speed of the buffered circuit, when driving large capacitive loads, to be increased. The disclosed masterslice cell, shown in the figure, contains a number of different size devices used for specific purposes when building logic functions. The cell contains 18 transistors: six p-channels and twelve n-channels. This allocation of devices allows efficient implementation of level sensitive scan design (LSSD) latches using a minimum number of cells. This cell is unique because it provides devices optimized to perform specific functions in the cell.

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Buffered CMOS Masterslice Cell for Logic

This article describes a cell which allows the programmable use of either the conventional or buffered complementary metal oxide semiconductor (CMOS) circuit technique. This allows the speed of the conventional circuit, when driving small capacitive loads, and the speed of the buffered circuit, when driving large capacitive loads, to be increased. The disclosed masterslice cell, shown in the figure, contains a number of different size devices used for specific purposes when building logic functions. The cell contains 18 transistors: six p-channels and twelve n-channels. This allocation of devices allows efficient implementation of level sensitive scan design (LSSD) latches using a minimum number of cells. This cell is unique because it provides devices optimized to perform specific functions in the cell. Devices A-H are arranged in p-n pairs for building elementary logic functions, such as NAND, NOR, etc. Devices J-M are larger p-n pairs used in output buffers to increase the drive capability of logic books. Devices N-S are n-channels used only in latches. Being a masterslice, every cell on the chip will contain these devices, which will then be connected together with metal to perform the various functions. In this product, all levels up through contacts are standard; only the two metal layers and the via between them are personalized. This reduces turnaround time in implementing a logic design on this chip. By placing buffer devices in every cell, every book in the chip's library may have high output drive capability, without adding complexity to the automatic placement and wiring programs. That is, in most gate arrays, if the designer needs to drive a large capacitive load, an extra cell must be consumed to build a high-power buffer to connect to the book's output. This requires reshuffling the first pass of the automatically placed books in order to...