Browse Prior Art Database

Stacked Dense CMOS RAM Using Silicon on Insulator Technology

IP.com Disclosure Number: IPCOM000044208D
Original Publication Date: 1984-Nov-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Bertin, CL: AUTHOR [+2]

Abstract

A dense, low power, fast static RAM (random-access memory) is fabricated using silicon on insulator technology. The device uses a stacked CMOS flip-flop as the storage element and stacked N or P channel field-effect transistors (FETs) as the transfer devices. A first set of devices is formed in silicon, while a second set of devices is formed in recrystallized polysilicon. The recrystallized polysilicon devices overlie the silicon devices to form the stacked RAM, with shared common gates. Fig. 1 shows the circuit diagram of a completely stacked CMOS RAM cell. Transistors T1 and T2, which may be either N or P channel FETs, serve as the transfer devices. Transistors T3, T4, T5, and T6 are connected in a flip-flop configuration, thus forming the storage device of the RAM cell.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 87% of the total text.

Page 1 of 2

Stacked Dense CMOS RAM Using Silicon on Insulator Technology

A dense, low power, fast static RAM (random-access memory) is fabricated using silicon on insulator technology. The device uses a stacked CMOS flip-flop as the storage element and stacked N or P channel field-effect transistors (FETs) as the transfer devices. A first set of devices is formed in silicon, while a second set of devices is formed in recrystallized polysilicon. The recrystallized polysilicon devices overlie the silicon devices to form the stacked RAM, with shared common gates. Fig. 1 shows the circuit diagram of a completely stacked CMOS RAM cell. Transistors T1 and T2, which may be either N or P channel FETs, serve as the transfer devices. Transistors T3, T4, T5, and T6 are connected in a flip-flop configuration, thus forming the storage device of the RAM cell. Transistors T3 and T6 are N channel devices, while transistors T4 and T5 are P channel devices. Nodes 7 and 8 are common to both N and P channel transistors. Fig. 2 shows the layout of transistors T1, T3, and T6 which serve as the lower devices in the stacked CMOS array. The cross-hatched areas in Fig. 2 indicate areas of silicon diffusion. Thus, transistors T1, T3, and T6 are formed in the lower silicon substrate. Areas 9 and 10 are first level polysilicon. Area 11 is second level polysilicon. Fig. 3 shows the layout of transistors T2, T4, and T5. The hatched areas in Fig. 3 represent recrystallized polysilicon diffusions. Thus, tra...