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Patchable Read-Only Storage and Other Patchable Functions

IP.com Disclosure Number: IPCOM000044210D
Original Publication Date: 1984-Nov-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Bertin, CL: AUTHOR [+3]

Abstract

A memory architecture is described in which an alterable PLA (programmable logic array) and a ROS (read-only storage) or a RAM (random-access memory) have inputs and outputs which are connected in parallel. The parallel connection allows the PLA to inhibit memory data at a given address in either the ROS or the RAM, while providing user-edited data for the given address in ROS or RAM. The use of a PLA in this manner eliminates the need for changes in the microcode as a result of errors in either ROS or RAM. These microcode changes usually require the use of PROM (programmable read-only memory) or EEROM patch cards which are very expensive on a per bit basis and also inconvenient to install. The ROS patch feature is included directly on the ROS chip and is in parallel with the ROS functions.

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Patchable Read-Only Storage and Other Patchable Functions

A memory architecture is described in which an alterable PLA (programmable logic array) and a ROS (read-only storage) or a RAM (random-access memory) have inputs and outputs which are connected in parallel. The parallel connection allows the PLA to inhibit memory data at a given address in either the ROS or the RAM, while providing user-edited data for the given address in ROS or RAM. The use of a PLA in this manner eliminates the need for changes in the microcode as a result of errors in either ROS or RAM. These microcode changes usually require the use of PROM (programmable read-only memory) or EEROM patch cards which are very expensive on a per bit basis and also inconvenient to install. The ROS patch feature is included directly on the ROS chip and is in parallel with the ROS functions. The parallel path is formed using a nonvolatile, alterable PLA macro where the AND array of the PLA performs an associative function and intercepts the address to be altered on the ROS as shown in Fig. 1. Each product term line contains an address whose data is to be altered. The product terms drive the alterable OR array which contains the altered data. An extra output line in the OR array generates a signal which inhibits ROS array output when an address is identified for data alteration. The size of the alterable nonvolatile PLA that is to be used is determined by the number of addresses in ROS which are to be modified. For a 144-kilobit ROS, using two alterable bytes per 1000 bytes of ROS (9 bits to a byte), the PLA AND array will have 32 product terms capable of accommodating 32 addresses in ROS. The address input is 14 bits with 28 AND array input lines to provide both true and complement lines. The total number of AND array alterable bit locations is thus 896 (28x32). The addresses in ROS to be modified are stored, one per product term, as the complement...