Browse Prior Art Database

SEM Voltage-To-Phase Contrast Converter

IP.com Disclosure Number: IPCOM000044221D
Original Publication Date: 1984-Nov-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Aufrere, J: AUTHOR [+3]

Abstract

A voltage-to-phase converter is used in conjunction with a scanning electron microscope (SEM) to visualize, in black and white on a cathode ray tube screen, the in and out of phase voltages with respect to a reference signal in a chip. The phase-dependent voltage contrast method which is used for large-scale integrated (LSI) circuit failure analysis requires a processing of the video signal by means of a phase detection module which is placed between the secondary electron detector control circuit (SDC) and the video detector control circuit (VDC) of a SEM. The light contrast obtained on the screen is proportional to the phase difference between the signals in the chip or device under test (DUT) and a clock signal which is used as a reference signal. All the potentials are visualized with a grey level.

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SEM Voltage-To-Phase Contrast Converter

A voltage-to-phase converter is used in conjunction with a scanning electron microscope (SEM) to visualize, in black and white on a cathode ray tube screen, the in and out of phase voltages with respect to a reference signal in a chip. The phase-dependent voltage contrast method which is used for large-scale integrated (LSI) circuit failure analysis requires a processing of the video signal by means of a phase detection module which is placed between the secondary electron detector control circuit (SDC) and the video detector control circuit (VDC) of a SEM. The light contrast obtained on the screen is proportional to the phase difference between the signals in the chip or device under test (DUT) and a clock signal which is used as a reference signal. All the potentials are visualized with a grey level. Thus, the correct operation of a circuit can be rapidly detected. The phase contrast is obtained by inverting the video signal during the first half period of the clock signal and non-inverting this signal during the second half period. The clock signal is the phase reference and synchronizes the chip exercising signal with a variable delay. This delay allows the chip exercising signal to be set in or out of phase with respect to the clock signal and thus to see every signal on the chip, in black, white or grey, by adjustment of this delay. Two gates G1 and G2 are controlled by the clock signal 0 and -0/ so that either the vi...