Browse Prior Art Database

Method for the Formation of an FET Depletion-Mode Load Device With a Buried Contact

IP.com Disclosure Number: IPCOM000044222D
Original Publication Date: 1984-Nov-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 3 page(s) / 50K

Publishing Venue

IBM

Related People

Fredericks, EC: AUTHOR [+3]

Abstract

A sequence of figures is shown illustrating the process for the formation of an FET (field-effect transistor) depletion-mode load device with a buried contact. Fig. 1 shows a first stage of the process invention, which starts with the recessed oxide layers 4 and 4' having already been formed on the surface of the silicon substrate 2 of P-type conductivity, thereby defining a device region 1. A layer of thin gate oxide 6 is formed on the surface of the silicon substrate between the recessed oxide regions 4 and 4'. A layer of photoresist 8 is uniformly deposited over all exposed surfaces of the assembly. The process for patterning the photoresist layer is to include exposure by an electron beam.

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Method for the Formation of an FET Depletion-Mode Load Device With a Buried Contact

A sequence of figures is shown illustrating the process for the formation of an FET (field-effect transistor) depletion-mode load device with a buried contact.

Fig. 1 shows a first stage of the process invention, which starts with the recessed oxide layers 4 and 4' having already been formed on the surface of the silicon substrate 2 of P-type conductivity, thereby defining a device region 1. A layer of thin gate oxide 6 is formed on the surface of the silicon substrate between the recessed oxide regions 4 and 4'. A layer of photoresist 8 is uniformly deposited over all exposed surfaces of the assembly. The process for patterning the photoresist layer is to include exposure by an electron beam. The electron beam is adjusted during a first stage of the exposure so as to expose a relatively large area indicated by the numeral 8' to a depth of approximately one-half of the total thickness of the photoresist layer 8. In a second stage of the electron beam exposure step, a deeper exposure is made at the location 10 in order to expose the photoresist layer 8 completely through to the gate oxide layer 6 and the recessed oxide layer 4. This step of the dual exposure of the region 1 would typically require two masking steps in the prior art. However, with a suitable adjustment of the electron beam during the first stage, a partial depth exposure of the photoresist 8 can be carried out so as to enable the removal of the portion 8' of the photoresist and then a deeper exposure of the same photoresist layer 8 can be carried out in the region 10 in order to completely penetrate the photoresist layer 8. This improvement allows a self-registration between the region 10 and the larger region represented by 8'. As will be seen further on in this article, region 10 will be the portion of the device having the buried contact and the region corresponding to 8' will be the portion including the depletion- mode FET channel. Fig. 2 shows the next step in the process wherein the portion 6' of the thin gate...