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Gated Pulse Generator for Pulses With Adjustable Delay and Width

IP.com Disclosure Number: IPCOM000044225D
Original Publication Date: 1984-Nov-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Pamminger, WR: AUTHOR

Abstract

An improved gated pulse generator is proposed which, by employing two flip-flops and XORing their outputs, eliminates deadtime problems. In test equipment, pulses must be programmable relative to a start time To, i.e., the pulse delay relative to To and the pulse width must be adjustable. This has been realized so far by a start pulse (delay) and a stop pulse (width) which are connected to the clock and reset inputs of an edge-triggered D-type flip-flop. For this purpose, only one (mostly the clock) input is edge-triggered, whereas the other input, in addition to being the dominant one, is level-triggered. As a result, the flip-flop is inactive for the time the dominant pulse is active. The start pulse is even suppressed if it overlaps the dominant stop pulse. Fig.

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Gated Pulse Generator for Pulses With Adjustable Delay and Width

An improved gated pulse generator is proposed which, by employing two flip- flops and XORing their outputs, eliminates deadtime problems. In test equipment, pulses must be programmable relative to a start time To, i.e., the pulse delay relative to To and the pulse width must be adjustable. This has been realized so far by a start pulse (delay) and a stop pulse (width) which are connected to the clock and reset inputs of an edge-triggered D-type flip-flop. For this purpose, only one (mostly the clock) input is edge-triggered, whereas the other input, in addition to being the dominant one, is level-triggered. As a result, the flip-flop is inactive for the time the dominant pulse is active. The start pulse is even suppressed if it overlaps the dominant stop pulse. Fig. 1 illustrates by way of three pulse cycles some relative positions of the start/stop pulses. It shows that in cycle 2, the expected output pulse (broken lines) does not appear, because start and stop pulses overlap each other, and the stop pulse is the dominant one. The circuit shown in the schematic of Fig. 2, which comprises two flip-flops FF1 and FF2, whose outputs are XORed, eliminates the flip-flop deadtime by means of a level-triggered RESET pulse. Start pulse (clock 1) and stop pulse (clock 2) act on the edge-triggered clock inputs of FF1 and FF2. The outputs Q1 and Q2 are connected by an XOR gate, so that each change in their sta...