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Microprocessor Base/Displacement Addressing Instructions

IP.com Disclosure Number: IPCOM000044229D
Original Publication Date: 1984-Nov-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 7 page(s) / 83K

Publishing Venue

IBM

Related People

Barber, JA: AUTHOR [+6]

Abstract

Base displacement/indirect addressing instructions are added to an existing microprocessor architecture, such as the IBM System/32 and System/34, which have fixed length instruction sets. This is done without impacting existing instructions. In the past many microprocessors did not support Base/Displacement addressing due to the limited length of the instruction (i.e., fixed-length instructions with no bits available for Displacement value specifications). This practice has been necessary because the additional bits required for specifying the Base Register and Displacement fields either detract from the ability to support other needed functions or require that the instruction word length be expanded sufficiently to include the additional fields.

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Microprocessor Base/Displacement Addressing Instructions

Base displacement/indirect addressing instructions are added to an existing microprocessor architecture, such as the IBM System/32 and System/34, which have fixed length instruction sets. This is done without impacting existing instructions. In the past many microprocessors did not support Base/Displacement addressing due to the limited length of the instruction (i.e., fixed-length instructions with no bits available for Displacement value specifications). This practice has been necessary because the additional bits required for specifying the Base Register and Displacement fields either detract from the ability to support other needed functions or require that the instruction word length be expanded sufficiently to include the additional fields. Prior arrangements use bits within each instruction to designate whether or not the instruction requires one or more Base-plus-Displacement address computations(s). These bits might be provided as part of the instruction op code itself or as modifiers to the op code. This increases the number of bits needed to specify an operation. Even in the simplest application, at least one extra bit is required for specifying whether or not a particular operation should be performed using Base/Displacement addressing. Any bits used strictly for this purpose constitute overhead for those instructions not utilizing Base/ Displacement addressing. The present arrangement uses a control latch in the hardware combined with a single instruction op code to designate whether or not a Base- plus-Displacement address computation is required. The op code is common to all Base/Displacement instructions. This instruction op code is shared by two totally different instruction types--one requiring Base/Displacement addressing and one not requiring Base/Displacement addressing. This is possible through the use of the Base/Displacement control latch. Further, in the present arrangement, more than one storage, i.e., main or control storage, can be specified for access. Timings and control logic are simplified by doing the computation in an operation common to all Base/Displacement instructions and performing it before decoding the particular function to be performed. Timings and control, then, are virtually identical for like functions, those which use Base/Displacement addressing and those which do not. Base displacement and non-base displacement instructions are shown in Fig. 1. The non-base displacement instruction performs the function specified in the field defined by Bits 8-11 using operand registers specified by the REG1 and REG2 fields. In general, the results are written into REG1. H1 and H2 specify the HI/LO byte of the associated operand registers. The base displacement instruction performs the function specified in the field defined by Bits 8-11 of the second word using REG1 as one operand and using the data fetched from storage as the second operand....