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Control Acquisition Sequence for IEEE P896 Bus

IP.com Disclosure Number: IPCOM000044246D
Original Publication Date: 1984-Nov-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 79K

Publishing Venue

IBM

Related People

Taub, DM: AUTHOR

Abstract

An asynchronous arbitration mechanism for devices seeking to gain control of the bus in an IEEE P896 computer bus system is described by D. M. Taub in IEEE Colloquium Digest No. 1983-95 entitled "A Preview of the IEEE P896 Draft Specification". The present article discloses an alternative which eliminates the arbitration process when there is only one requestor and avoids the possibility of transferring control to a requestor whose priority is not the highest. The IEEE P896 is a proposed standard computer bus designed to interconnect multimicroprocessor systems including their peripheral devices, common storage, etc. Before any device can initiate a data transfer, it has to gain control of the bus.

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Control Acquisition Sequence for IEEE P896 Bus

An asynchronous arbitration mechanism for devices seeking to gain control of the bus in an IEEE P896 computer bus system is described by D. M. Taub in IEEE Colloquium Digest No. 1983-95 entitled "A Preview of the IEEE P896 Draft Specification". The present article discloses an alternative which eliminates the arbitration process when there is only one requestor and avoids the possibility of transferring control to a requestor whose priority is not the highest. The IEEE P896 is a proposed standard computer bus designed to interconnect multimicroprocessor systems including their peripheral devices, common storage, etc. Before any device can initiate a data transfer, it has to gain control of the bus. As two or more devices may seek to do this at the same time an arbitration system is required to decide which of them shall succeed first. These devices are termed Potential Masters (PMs), each of which is allocated an n-bit arbitration number (AN) unique to itself which it may transmit on arbitration lines within the bus. When a PM has gained control of the bus, it becomes the Current Master (CM). Arbitration can take place during the CM's tenure of the bus, and the winner is called the Next Master (NM). The scheme described in the reference cited above is optimized so that when arbitration is carried out concurrently with a data transaction, handover of control to the NM at the end of CM's tenure takes place in the shortest possible time. However, in certain other respects the scheme is sub-optimal, for instance: a) The arbitration process has to be gone through even when there is only one contender for the bus. If the bus is idle at the time, this involves an unnecessary delay. b)

If arbitration takes place concurrently with a data...