Browse Prior Art Database

Patch RAM Load Technique

IP.com Disclosure Number: IPCOM000044252D
Original Publication Date: 1984-Nov-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Sibbers, DE: AUTHOR [+2]

Abstract

In the context of I/O controllers, microprocessors with read-only memory (ROM) are often used for implementation. During early field experience it may be necessary to provide a means to quickly circumvent unexpected "bugs" in the microcode. One way to do this is to provide a smaller random-access memory (RAM) in parallel with the ROM and switch to RAM where microcode changes are required. A particular way to do this is to substitute blocks of RAM, called Pages, which essentially duplicate the code in the ROM except for those instructions which require modification. In this system, the low-order bits of a control store address are fed to the patch RAM 1 via bus 2 connected to an address register (not shown).

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Patch RAM Load Technique

In the context of I/O controllers, microprocessors with read-only memory (ROM) are often used for implementation. During early field experience it may be necessary to provide a means to quickly circumvent unexpected "bugs" in the microcode. One way to do this is to provide a smaller random-access memory (RAM) in parallel with the ROM and switch to RAM where microcode changes are required. A particular way to do this is to substitute blocks of RAM, called Pages, which essentially duplicate the code in the ROM except for those instructions which require modification. In this system, the low-order bits of a control store address are fed to the patch RAM 1 via bus 2 connected to an address register (not shown). The high-order bits of the address are fed to table lookup RAM 3 via bus 4 which is connected to the address register (not shown). The entire control store address is also applied to ROM 5 through bus 6. When the table lookup RAM 3 detects that a Page address with invalid ROM data has been selected, the output of inverter 7 causes the output of ROM 5 to be inhibited and the output of the patch RAM 1 to be substituted on the control store data bus 8. Loading of both the table lookup RAM and the Patch RAM utilizes the existing Address connections. In addition, the processor data bus is connected to the data inputs. In order to write either RAM, the address and data lines must be properly conditioned, the desired RAM selected, and a write access cycle taken. In this system these conditions are uniquely provided by a minor modification to an existing processor instruction. A Return From Subroutine instruction fetches a return address and branches to that address. A simple modification to this instruction causes it to access the local store memory and put the data on the controller bus which then conditions the data inputs to the patch RAM 1. Normally the processor would branch to the...