Browse Prior Art Database

Automatic Delay Increase/Decrease Testing for FET Memories

IP.com Disclosure Number: IPCOM000044255D
Original Publication Date: 1984-Nov-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Gray, KS: AUTHOR

Abstract

Current field-effect transistor (FET) dynamic RAM (DRAM) chips have on-chip timing chains made up of delay stages and drivers. This article describes a method that, by applying a variable DC voltage to one of two test pads or test points, changes the individual delays of all the delay stages on the chip. The change can be either an increase or decrease, and will be a variable percentage change of all delay stage delays. In normal operation the two test pads or test points are floating or held to the voltage (VH) potential and the operation of the delay stages will not be affected. The feature is shown incorporated into a typical delay stage where the dashed lines at the bottom of the diagram represent the devices that implement this feature.

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Automatic Delay Increase/Decrease Testing for FET Memories

Current field-effect transistor (FET) dynamic RAM (DRAM) chips have on-chip timing chains made up of delay stages and drivers. This article describes a method that, by applying a variable DC voltage to one of two test pads or test points, changes the individual delays of all the delay stages on the chip. The change can be either an increase or decrease, and will be a variable percentage change of all delay stage delays. In normal operation the two test pads or test points are floating or held to the voltage (VH) potential and the operation of the delay stages will not be affected. The feature is shown incorporated into a typical delay stage where the dashed lines at the bottom of the diagram represent the devices that implement this feature. Normally, the source of T13 is connected to ground and the drain of T14 is connected to VH. Device TA is added once per delay stage. The VHI test pad, resistor RA and the decoupling capacitor CA are added once per chip, and fan out to all the TA devices. Device TB, the VHD test pad, resistor RB and the decoupling capacitor CB are added once per chip and the source of TB is fanned out to the DRAMs of all the existing T14 devices. In normal operation, VHD and VHI are floating or held at VH potential. If a voltage is applied to VHI and lowered below VH, the delays of all delay stages will increase by a percentage that is determined by the VHI level. If a voltage is appli...