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Back Gate Control Circuits

IP.com Disclosure Number: IPCOM000044257D
Original Publication Date: 1984-Nov-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Leighton, HN: AUTHOR

Abstract

Back gate control circuits can be used for both P and N type JFETs (junction field-effect transistors) to maintain a constant Vt, and also to maintain other selected operating points via back gate control. Further, this concept is not restricted to JFETS, but may also be applied to both p- and n-channel MOSFETs (metal oxide semiconductor field-effect transistors) as long as they have a separate back gate.A novel application of back gate control to achieve differential pair offset compensation is shown in the figure. Transistors Q1 and Q2 are the differential pair to be precision matched for low offset. Transistor Q3 is a current source for the differential pair which is back gate controlled via transistor Q4 and amplifier A1 to deliver an output current Io' ~ Io .

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Back Gate Control Circuits

Back gate control circuits can be used for both P and N type JFETs (junction field-effect transistors) to maintain a constant Vt, and also to maintain other selected operating points via back gate control. Further, this concept is not restricted to JFETS, but may also be applied to both p- and n-channel MOSFETs (metal oxide semiconductor field-effect transistors) as long as they have a separate back gate.A novel application of back gate control to achieve differential pair offset compensation is shown in the figure. Transistors Q1 and Q2 are the differential pair to be precision matched for low offset. Transistor Q3 is a current source for the differential pair which is back gate controlled via transistor Q4 and amplifier A1 to deliver an output current Io' ~ Io . The combination of transistors Q3, Q4 and amplifier A1 is one example of an implementation of the general concept. VB is a common front gate bias voltage for both transistors Q3 and Q4. With the front gates of both transistors Q1 and Q2 connected to a common voltage, such as ground, Va - Vb = Ve= O for zero offset. This means that I1R1 = I2R2, where I1=IDS of Q1, and I2=IDS of Q2 . One offset compensation method in use is to trim R1 or R2 . When R1 =/ R2, the differential pair will suffer a degradation in common mode rejection (CMR) and gain balance. A method that avoids those degradations is to trim I2 relative to I1 via back gate control. Either VG1 is kept fixed and VG2 is varied to achieve I1R1 =...