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Realtime Wafer Characterization for Maintaining Maximum Registration Accuracy and Maximum Tool Throughput

IP.com Disclosure Number: IPCOM000044259D
Original Publication Date: 1984-Nov-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Babinski, JP: AUTHOR

Abstract

The trends in integrated circuit product ground rules impose tighter requirements on resolution and registration accuracy from the optical-lithographic equipment. This article describes a new technique which uses the step and repeat (S/R) die by die alignment system as a measurement station to gather "realtime" overlay data from the first wafer of a lot and uses this information with the developed algorithms to: o Compile a real time overlay wafer map of the wafer being aligned and exposed. o Calculate source of overlay errors and feed this information back to the S/R tool for realtime corrective action if desired. o Calculate which die(s) are within programmable overlay limits and direct the S/R system to align only those die(s) that are out of range.

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Realtime Wafer Characterization for Maintaining Maximum Registration Accuracy and Maximum Tool Throughput

The trends in integrated circuit product ground rules impose tighter requirements on resolution and registration accuracy from the optical-lithographic equipment. This article describes a new technique which uses the step and repeat (S/R) die by die alignment system as a measurement station to gather "realtime" overlay data from the first wafer of a lot and uses this information with the developed algorithms to: o Compile a real time overlay wafer map of the wafer being aligned and exposed. o Calculate source of overlay errors and feed this information back to the S/R tool for realtime corrective action if desired. o Calculate which die(s) are within programmable overlay limits and direct the S/R system to align only those die(s) that are out of range. o Maintain a file of all wafer maps (if desired) which can be used to analyze the 1X scan projection systems. In operation, the algorithm uses the die by die information obtained on the first wafer of the lot to calculate the fix errors (Mx, My) caused by 1X tool magnification, process induced magnification errors, 1X mask step errors and any alignment offsets induced by the auto align system (X, Y), and feeds these corrections back to the S/R system operating software prior to the aligning and exposing of the second wafer of the lot. It is important to note that the above calculations would take place during t...