Browse Prior Art Database

I2L Selector Circuit

IP.com Disclosure Number: IPCOM000044264D
Original Publication Date: 1984-Nov-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Wong, RC: AUTHOR

Abstract

Selector circuits are used in many logic applications. The selector function may be expressed as follows: S = CA + CB where A is selected when C is down, and B is selected when C is up. In conventional implementations, two to three stages of logic gates are used. In some logic families, special circuits have been proposed and used to realize this function in one stage. Fig. 1 is an I2L selector circuit implementation. In Fig. 2, input C serves as the variable circuit bias and provides the select function. Fig. 3 is a hazard-free selector circuit. In both Figs. 1 and 2, logic hazard may occur if A=1, B=1, C=0 and C is rising to 1, or C=1 and falling to 0. The hazard is eliminated by employing the circuit of Fig. 3. In Figs. 2 and 3, multiple fanouts of the control signal C are also possible.

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I2L Selector Circuit

Selector circuits are used in many logic applications. The selector function may be expressed as follows: S = CA + CB where A is selected when C is down, and B is selected when C is up. In conventional implementations, two to three stages of logic gates are used. In some logic families, special circuits have been proposed and used to realize this function in one stage. Fig. 1 is an I2L selector circuit implementation. In Fig. 2, input C serves as the variable circuit bias and provides the select function. Fig. 3 is a hazard-free selector circuit. In both Figs. 1 and 2, logic hazard may occur if A=1, B=1, C=0 and C is rising to 1, or C=1 and falling to 0. The hazard is eliminated by employing the circuit of Fig. 3. In Figs. 2 and 3, multiple fanouts of the control signal C are also possible.

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