Browse Prior Art Database

Viewport Priority Circuit

IP.com Disclosure Number: IPCOM000044282D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Gohda, Y: AUTHOR [+2]

Abstract

The present circuit determines priority among a plurality of viewports which are to be simultaneously displayed on the same screen. Each of the viewports is identified by a unique viewport ID consisting of n bits. Thus, up to 2n viewports can be distinguished from each other. When it is desired to simultaneously display a plurality of viewports, n-bit priority registers 10 are loaded with the viewport ID's thereof in accordance with a predetermined priority. A viewport ID loaded into a priority register 0 has the highest priority, while a viewport ID loaded into a priority register 2n - 1 has the lowest priority. The smaller the priority register number, the higher the priority. If a viewport ID of a selected viewport is loaded into all the priority registers, the other viewports would never be displayed.

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Viewport Priority Circuit

The present circuit determines priority among a plurality of viewports which are to be simultaneously displayed on the same screen. Each of the viewports is identified by a unique viewport ID consisting of n bits. Thus, up to 2n viewports can be distinguished from each other. When it is desired to simultaneously display a plurality of viewports, n-bit priority registers 10 are loaded with the viewport ID's thereof in accordance with a predetermined priority. A viewport ID loaded into a priority register 0 has the highest priority, while a viewport ID loaded into a priority register 2n - 1 has the lowest priority. The smaller the priority register number, the higher the priority. If a viewport ID of a selected viewport is loaded into all the priority registers, the other viewports would never be displayed. Associated with each of the priority registers 10 are a set of n AND gates 12 and a multiplexer 14. Each of the AND gates receives a corresponding bit of the viewport ID stored in the associated priority register. The multiplexer is enabled to pass a corresponding viewport display enable signal. For example, if a viewport ID of a second viewport (VP1) has been loaded into the priority register 0, a first multiplexer (MUX 0) passes a viewport 1 display enable signal (VP1 DISP EN). Corresponding image information (VP1 IMAGE INFO) is provided to an output multiplexer (MUX) 16. The image information may be a memory address, a cursor signal,...