Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

CMOS Half-Latch Circuits

IP.com Disclosure Number: IPCOM000044284D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

Carlile, PS: AUTHOR

Abstract

In dynamic RAMs, a word line is turned off by the word line driver, but a half latch is required to hold it in the off state. These latches require a reset signal which complicates timing and layout. A complementary metal oxide semiconductor (CMOS) half-latch is designed to clamp a word line off for either a p- or n-channel array while eliminating the need for the reset signal. For an n-channel array (Fig. 1), when the word line is low, node A is high, thus turning T3 on and clamping the word line to ground. When the word line is driven high, node A falls shutting T3 off. In the case of a p-channel (Fig. 2), just the opposite occurs. When the word line is high in an off state, node A is low, thus turning the p-channel T3 on, holding the word line high. When the word line is pulled low, node A rises and turns T3 off.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

CMOS Half-Latch Circuits

In dynamic RAMs, a word line is turned off by the word line driver, but a half latch is required to hold it in the off state. These latches require a reset signal which complicates timing and layout. A complementary metal oxide semiconductor (CMOS) half-latch is designed to clamp a word line off for either a p- or n-channel array while eliminating the need for the reset signal. For an n- channel array (Fig. 1), when the word line is low, node A is high, thus turning T3 on and clamping the word line to ground. When the word line is driven high, node A falls shutting T3 off. In the case of a p-channel (Fig. 2), just the opposite occurs. When the word line is high in an off state, node A is low, thus turning the p-channel T3 on, holding the word line high. When the word line is pulled low, node A rises and turns T3 off.

1

Page 2 of 2

2

[This page contains 2 pictures or other non-text objects]