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Browse Prior Art Database

Clock Synchronization

IP.com Disclosure Number: IPCOM000044295D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Hennet, PP: AUTHOR [+3]

Abstract

Synchronizing a pair of receiver clock variable frequency oscillators upon alternate rises of the transmitted signal simplifies downstream circuitry. The problem to be solved consists of synchronizing a receiver clock by using only information contained in the transmitted signal. If the clock that sends the digital data (signal) is used to decode the data at the receiver, then another pair of wires (or a bus) is required to transmit the clock. Switching of the signal and clock is more difficult because of skew and because there are more switches. The clock is synchronized to the data at every transition of the signal, either positive (as shown) or negative; a signal protocol specifies that the signal will make a transition at least once every 6 clock cycles. The clock oscillators 1, 2 (Fig.

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Clock Synchronization

Synchronizing a pair of receiver clock variable frequency oscillators upon alternate rises of the transmitted signal simplifies downstream circuitry. The problem to be solved consists of synchronizing a receiver clock by using only information contained in the transmitted signal. If the clock that sends the digital data (signal) is used to decode the data at the receiver, then another pair of wires (or a bus) is required to transmit the clock. Switching of the signal and clock is more difficult because of skew and because there are more switches. The clock is synchronized to the data at every transition of the signal, either positive (as shown) or negative; a signal protocol specifies that the signal will make a transition at least once every 6 clock cycles. The clock oscillators 1, 2 (Fig. 1) are of the type that, once enabled, will transmit a full clock pulse even if the enable signal goes away, producing glitch-free clock pulses that are synchronized to every rising edge of the data. Each rising edge of the data toggles flip-flop 3 so that clock A1 is enabled and clock B2 is disabled, or vice-versa. The clock that is enabled will start off synchronized to the input signal rising edge. The OR gate 4 sums the signals of the two oscillators to provide the desired resynchronized "clock out." Fig. 2 shows the case where clock A is rising early, with respect to the input signal; Fig. 3 shows the case where clock A is rising late. The next toggl...