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Free-Running I/O With Overrun Termination

IP.com Disclosure Number: IPCOM000044300D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 3 page(s) / 75K

Publishing Venue

IBM

Related People

Brown, RP: AUTHOR

Abstract

A technique is described whereby continuous data may be supplied by a central processing unit (CPU) to an input/output (I/O) device that is capable of transferring large amounts of data without requiring large main storage buffers. I/O device applications which require the transfer of large quantities of unbroken, by time, data streams, occupy a high percentage of available storage as data buffers. I/O architecture that has the capability of allowing control blocks for multiple I/O functions to be chained together are utilized in this technique to provide a transfer capability which allows the use of multiple small buffers. The concept makes use of the chaining function by creating a closed loop of control blocks.

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Free-Running I/O With Overrun Termination

A technique is described whereby continuous data may be supplied by a central processing unit (CPU) to an input/output (I/O) device that is capable of transferring large amounts of data without requiring large main storage buffers. I/O device applications which require the transfer of large quantities of unbroken, by time, data streams, occupy a high percentage of available storage as data buffers. I/O architecture that has the capability of allowing control blocks for multiple I/O functions to be chained together are utilized in this technique to provide a transfer capability which allows the use of multiple small buffers. The concept makes use of the chaining function by creating a closed loop of control blocks. The asynchronous operation of CPU programs and attachment microcode provides the usefulness of this technique, so that once started with an I/O command, the attachment processes each device control block (DCB) in turn, and transfers data at its own rate. The application program and device handler in the CPU will process data at its own rate, which must be faster overall than the I/O attachment. The number of DCBs used will provide a flexible coupling between the attachment and the CPU. Should the CPU programs be slow in responding to the requirements of the attachment, there is sufficient data in the chain to allow the attachment to continue processing until the CPU is able to catch up. When the application program 10, as shown in logic data flow diagram Fig. 1, requests the device handler 11 to begin a transmit operation, device handler 11 transfers control information to the first DCB 12. Normally, a start I/O instruction would be issued to attachment 13. However, in this technique, the device handler 11 returns control back to the application program 10 for more data. When the application responds, the control information for this request is transferred to the next DCB 14, the first DCB 12 is chained to the second, as shown in Fig. 2. This sequence of operations will continue until the total number of DCBs minus one has been built, or until an ending request has been received from the application. Should an ending condition be encountered before reaching the nth DCB, device handler 11 will reset the chain indicator in the ending DCB and issue an I/O command to the attachment 13. In this case, attachment 13 will process each DCB and pass data to output 16. This operation will end in a normal manner when the DCB containing the ending function is encountered by attachment 13. When an n-1 condition is encountered and more data is...