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Prefetching Mechanism That Accommodates a Self-Modifying Code

IP.com Disclosure Number: IPCOM000044302D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 66K

Publishing Venue

IBM

Related People

Herrman, BD: AUTHOR [+2]

Abstract

A technique is described whereby control circuits are used in conjunction with computer storage circuits to provide a prefetching operation that allows self-modifying code. Assuming that prefetching operates on the principle that programs are executed sequentially through memory, storage circuitry is then able to prefetch instructions ahead of time. The access time is therefore reduced since the prefetched instructions are stored in high speed buffers. This procedure continues as long as the sequential flow of instructions is not broken by a branch or a jump. In a basic prefetching concept, when the central processing unit (CPU) requests an instruction from the storage card 10, as shown in Fig.

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Prefetching Mechanism That Accommodates a Self-Modifying Code

A technique is described whereby control circuits are used in conjunction with computer storage circuits to provide a prefetching operation that allows self- modifying code. Assuming that prefetching operates on the principle that programs are executed sequentially through memory, storage circuitry is then able to prefetch instructions ahead of time. The access time is therefore reduced since the prefetched instructions are stored in high speed buffers. This procedure continues as long as the sequential flow of instructions is not broken by a branch or a jump. In a basic prefetching concept, when the central processing unit (CPU) requests an instruction from the storage card 10, as shown in Fig. 1, the data from the high speed instruction buffer 11 is transmitted to the holding register 12 and then on to the logic gating circuitry 13 before going to the CPU. At the same time, the next sequential instruction is read from storage and placed in the high speed buffer 11, storing it for the next instruction fetch. Since there is the possibility that the CPU would issue a write cycle that modifies the next sequential instruction before the next instruction fetch cycle (i.e., the instruction in storage is modified but the value in the high speed buffer is not updated), this new concept, as shown in Fig. 2, was designed to maintain the prefetching advantages. The objective is to maintain the prefetched instruc...