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Logic and Decoder Arrangement for Controlling Spill/Wrap Boundaries of a Bit-Addressable Memory Decoder

IP.com Disclosure Number: IPCOM000044305D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 3 page(s) / 56K

Publishing Venue

IBM

Related People

Matick, RE: AUTHOR

Abstract

Logic and decoder structures are described for transferring data into and out of a memory organized in one specific manner, such as when a constant data path ND (e.g., ND = 16 bits) is provided to the memory and the data must start on any bit boundary. A decoder is required which provides bit addressability to any starting point, coupled with a parallel data path of 16 bits from any starting point. In typical application of CRT display architecture using a fixed data width in a bit-buffered memory, the screen format may have a minimum size of 512 by 512 pels, requiring a minimum of four memory chips (64K bits/chip) in a 2 by 2 array, as in Fig. 1. Each chip consists, logically, of 256 words by 256 bits/word: hence, the bits map in a one to one correspondence to the screen pels, as shown.

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Logic and Decoder Arrangement for Controlling Spill/Wrap Boundaries of a Bit-Addressable Memory Decoder

Logic and decoder structures are described for transferring data into and out of a memory organized in one specific manner, such as when a constant data path ND (e.g., ND = 16 bits) is provided to the memory and the data must start on any bit boundary. A decoder is required which provides bit addressability to any starting point, coupled with a parallel data path of 16 bits from any starting point. In typical application of CRT display architecture using a fixed data width in a bit- buffered memory, the screen format may have a minimum size of 512 by 512 pels, requiring a minimum of four memory chips (64K bits/chip) in a 2 by 2 array, as in Fig. 1. Each chip consists, logically, of 256 words by 256 bits/word: hence, the bits map in a one to one correspondence to the screen pels, as shown. The screen format can be expanded in the x or y direction by the addition of chips with a modularity of 256. The architecture may also allow the writing of 16 bits in parallel on each cycle, and is constant irrespective of screen format. The 16 data signals are ORed to all chips as well as an 8-bit binary word address (not shown) and an 8-bit/bit sense line address. A separate chip select signal is provided to each chip to form the final higher-order address selection function in the conventional manner. A give scan line is mapped to successive pels at a given Y axis word line, as in Fig. 1, and will cross the chip boundary in the X direction for the case illustrated. Since a character can start at any pel position and be up to 16 successive pels, it is necessary to be able to select any group of 16 pels in the X direction, starting at any pel boundary. It would also be desirable to be able to "wrap around" from the right-hand edge of the screen to the same scan line on the left-hand edge. This is quite unlike any other memory selection where typically a group of 8 or 16 bits is selected on an 8-bit boundary rather than on a one-bit boundary, as required here. In essence, this requires the superposition of 16 decoders each of which select one out of 256 bits. By proper arrangement and interconnection, a 16 out of 256 decoder, with addressability starting at any bit, can be provided, i.e., 256 choices of 16 bits, except for the right- and left- hand boundaries where special conditions occur (i.e., spillover and/or wrap around). The 16 out of 256-bit boundary decoder can be implemented in an array of 256 by 16 two-input AND gates. The AND gates could be simple FET devices with the gate serving as the control line and with source and drain serving as input and output, as shown in Fig. 2. This decoder by itself is essentially just the superposition of 16 conventional decoders, interconnected in a special manner with another 1 out of 256 decoder which selects the group of 16, starting at any bit. However, the right- and left-hand boundaries must pro...