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Programmable Clock Divider

IP.com Disclosure Number: IPCOM000044306D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Nahata, P: AUTHOR

Abstract

A technique is described whereby a counter and a digital magnitude comparator are utilized to divide a single base clock frequency into multiple clock frequencies for circuit application which require multiple clock frequencies derived from a single clock. At the beginning of the operation, counter 10, as shown in Fig. 1, is cleared and flip-flop 11 is reset. Counter 10 is incremented by "1" at the first leading edge 13 of the clock signal 12 shown in Fig. 2. The contents of counter 10 are then compared with the setting of comparator 14. If both values are equal, then A=B output 15 of the comparator becomes active and causes an output from flip-flop 11. If the compared values are not equal, A>B output 16 becomes active and flip- flop 11 stays reset.

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Programmable Clock Divider

A technique is described whereby a counter and a digital magnitude comparator are utilized to divide a single base clock frequency into multiple clock frequencies for circuit application which require multiple clock frequencies derived from a single clock. At the beginning of the operation, counter 10, as shown in Fig. 1, is cleared and flip-flop 11 is reset. Counter 10 is incremented by "1" at the first leading edge 13 of the clock signal 12 shown in Fig. 2. The contents of counter 10 are then compared with the setting of comparator 14. If both values are equal, then A=B output 15 of the comparator becomes active and causes an output from flip-flop 11. If the compared values are not equal, A>B output 16 becomes active and flip- flop 11 stays reset. At the next leading edge 17 of the clock, counter 10 is incremented again and the contents are again compared with the setting in comparator 14. If equal, A=B output 15 becomes active and A>B output 16 is inactive. When A=B output 15 is again active (18), flip-flop 11 is set, and counter 10 is cleared. At the next leading edge 19, counter 10 will count so that when A=B, output 15 becomes active, flip-flop 11 is toggled to the opposite state. The key to this idea is the counting of the clock frequency (clock transitions) in counter 10 and then comparing the contents of counter 10 with a preset value whereby frequency division is required plus "1" by the magnitude comparator 14. Counter 10 is...