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Anticipatory Carry Incrementor

IP.com Disclosure Number: IPCOM000044310D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Awsienko, O: AUTHOR [+2]

Abstract

A technique is described whereby a simple circuit is used to increment an address by four in one gate delay cycle utilizing a carry anticipatory approach. Therefore, it is possible to complete an entire full word incrementing operation in one cycle rather than requiring multiple cycles. When master and slave direct memory access (DMA) concepts are used in transferring data from one input/output bus unit (IOBU) to another, the second IOBU supplies the first IOBU with the memory starting address and the length of the transfer data. Due to misalignment in the master and slave addresses, adjustments are required to allow addresses on storage lines. During the first data cycle, the address is placed on the address lines as they are received.

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Anticipatory Carry Incrementor

A technique is described whereby a simple circuit is used to increment an address by four in one gate delay cycle utilizing a carry anticipatory approach. Therefore, it is possible to complete an entire full word incrementing operation in one cycle rather than requiring multiple cycles. When master and slave direct memory access (DMA) concepts are used in transferring data from one input/output bus unit (IOBU) to another, the second IOBU supplies the first IOBU with the memory starting address and the length of the transfer data. Due to misalignment in the master and slave addresses, adjustments are required to allow addresses on storage lines. During the first data cycle, the address is placed on the address lines as they are received. On the second data cycle, the address is required to be aligned on a word boundary and, for all subsequent data cycles, the address will be incremented by four so as to be kept on a word boundary. Since the address is aligned on a word boundary, the last two bits of the address are O,O. A "1" is added to the third least significant bit. Should the third least significant bit have been a zero, no carry is generated. If it was a "1," then a carry is generated and added to the next bit. Every time a carry is generated, a delay is introduced due to carry propagation to the next state. However, by anticipating the carry, carry propagation delay is eliminated. The incrementing-by-four concept uses three ex...