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Two-Dimensional Layout of Single-Ended Cvs Trees in Masterslice and Means for Realizing a Compact Master Image Layout Using Two-Dimensional Diffusion Wiring

IP.com Disclosure Number: IPCOM000044335D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 4 page(s) / 45K

Publishing Venue

IBM

Related People

Hauge, PS: AUTHOR [+2]

Abstract

The high functional density achievable with cascode circuit technology poses a challenge for designers to find circuit layouts which realize these high densities while still being wirable. In masterslice designs, single-ended cascode voltage switch (SCVS) circuits in particular are difficult to wire. This article describes a method to lay out SCVS circuits in a natural, two-dimensional array of transistors which attains high functional density and a means of using diffusion wiring also in two dimensions to enhance wirability. In the logical design of SCVS circuits, series/parallel (SP) orderings of transistors are encountered. Such circuits are more naturally realized as two-dimensional layouts than linear, one-dimensional layouts.

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Two-Dimensional Layout of Single-Ended Cvs Trees in Masterslice and Means for Realizing a Compact Master Image Layout Using Two- Dimensional Diffusion Wiring

The high functional density achievable with cascode circuit technology poses a challenge for designers to find circuit layouts which realize these high densities while still being wirable. In masterslice designs, single-ended cascode voltage switch (SCVS) circuits in particular are difficult to wire. This article describes a method to lay out SCVS circuits in a natural, two-dimensional array of transistors which attains high functional density and a means of using diffusion wiring also in two dimensions to enhance wirability. In the logical design of SCVS circuits, series/parallel (SP) orderings of transistors are encountered. Such circuits are more naturally realized as two-dimensional layouts than linear, one-dimensional layouts. In masterslice designs, a two-dimensional layout may be achieved by a procedure described here, but such layouts (called "trees") are found to be difficult to wire when only two planes of metal are available. Following a series of steps described here-in, a two-dimensional masterslice design may be migrated to a master image design in which a large fraction or all of its INTERNAL tree connections may be made in diffusion. This procedure is advantageous since increasing the use of diffusion increases the number of metal wiring tracks available for making global tree connections. The method described makes maximal use of diffusion to wire internal tree connections. The method comprises a procedure for laying out the transistors in a natural series-parallel arrangement, providing connection between both vertically and horizontally adjacent transistors with diffusion, and compacting the diffusion-wired tree vertically to achieve maximum functional density. A SCVS tree is a collection of FET transistors connected between a CLOCK and a LOAD device. The transistor connectivity is given by a master logic list (MLL) or low-level description language (BDL/S). From the connectivity the SP ordering is algorithmically derived. Such an ordering is shown in Fig. 1. The ordering algorithm is described briefly as follows: The transistors which connect to the clock in parallel are placed on the bottom row of the tree. Transistors connected in series with those in the bottom row are placed on the second row, directly above the connecting transistor. This process is repeated each row in the tree (typically 5). Occasionally, some of the previously placed transistors must be repositioned. When first placed, each transistor is as low and as far to the left as possible, consistent with the previously placed transistors. It sometimes occurs that a row has more transistors locally than a lower, previously placed row. In that case, in order to maintain alignment of vertically adjacent transistors, each transistor located below and to the right of the congested location is mo...