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Cascode Voltage Switch Logic

IP.com Disclosure Number: IPCOM000044341D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Erdelyi, CK: AUTHOR [+3]

Abstract

The Cascode Voltage Switch Logic (CVSL) circuit utilizing all NMOS FET devices is illustrated in Fig. 1. S1,S2 represent the interconnected N channel FET devices that provide a conductive path between the common node and N1 or N2, but never at the same time. Logical signals control which of the two paths will conduct at a given time. I1,I2 are inverters/buffers whose purpose is to change the logical levels provided by N1 and N2 to the opposite polarity in order to drive T1 and T2. An additional purpose is to provide the capability for driving loads connected to the output nodes of the circuit, F and F. T1,T2 are the N channel FETs that provide the pullup for nodes N1 and N2 whenever S1 or S2 allows one of these nodes to rise. These devices may be enhancement, zero volt threshold (0 VT), or depletion mode devices.

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Cascode Voltage Switch Logic

The Cascode Voltage Switch Logic (CVSL) circuit utilizing all NMOS FET devices is illustrated in Fig. 1. S1,S2 represent the interconnected N channel FET devices that provide a conductive path between the common node and N1 or N2, but never at the same time. Logical signals control which of the two paths will conduct at a given time. I1,I2 are inverters/buffers whose purpose is to change the logical levels provided by N1 and N2 to the opposite polarity in order to drive T1 and T2. An additional purpose is to provide the capability for driving loads connected to the output nodes of the circuit, F and F. T1,T2 are the N channel FETs that provide the pullup for nodes N1 and N2 whenever S1 or S2 allows one of these nodes to rise. These devices may be enhancement, zero volt threshold (0 VT), or depletion mode devices. The circuit is operated as follows: Assume the initial state in which S1 is closed and S2 is open. N1 is at a down level, and N2 is at an up level. T2 is conducting, and T1 is turned off, which is assured by F being at a low level and F at a high level due to the action of I1 and I2. The only DC current that is flowing is through I2, unless T1,T2 are depletion devices. Due to the change of the logical inputs, the states of S1 and S2 become reversed; that is, S2 closes and S1 opens. Since S2 closed represents a smaller resistance than T2, N2 is pulled down. This causes F to rise, turning on T1, which causes N1 to be pulled up. N1 being pulled up causes I1 to pull down F, which turns of...