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Reducing AGI in Loops

IP.com Disclosure Number: IPCOM000044353D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Emma, PG: AUTHOR [+5]

Abstract

Pipelined processors incur a delay when the register(s) required to decode instructions are not available. These delays are reduced by utilizing the method set forth below. Given a sequence of instructions which are repeated and which contain a register setting and register using instruction such that an interlock occurs [address generate interlock (AGI)], it is possible to eliminate such interlocks on subsequent iterations of the loop as follows: Consider the following loop: (Image Omitted) The last setting of the monitored register is determined within the loop, and the address generate (AGEN) and operand fetch (in case the AGIing instruction is a Load) associated with the AGIing instruction are performed. This operand fetch is then used to avoid AGI in the loop on a putative basis until it is validated.

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Reducing AGI in Loops

Pipelined processors incur a delay when the register(s) required to decode instructions are not available. These delays are reduced by utilizing the method set forth below. Given a sequence of instructions which are repeated and which contain a register setting and register using instruction such that an interlock occurs [address generate interlock (AGI)], it is possible to eliminate such interlocks on subsequent iterations of the loop as follows: Consider the following loop:

(Image Omitted)

The last setting of the monitored register is determined within the loop, and the address generate (AGEN) and operand fetch (in case the AGIing instruction is a Load) associated with the AGIing instruction are performed. This operand fetch is then used to avoid AGI in the loop on a putative basis until it is validated. Any serializing event will invalidate this action. Once an AGI is detected, the AGEN- image and the AGIing instruction is recorded. All setting instructions of the monitored register induce AGEN AND OPERAND FETCHES during the first iteration. If X=Y (i.e., the AGIing instruction sets the AGIed register), the operand refetch with the updated register is immediate. The last setting of the monitored register is the only one which is required to AGEN on subsequent iterations. In a machine which does not prefetch targets of taken branches, the mechanism for reduction can be simplified so that the operand fetch action is overlapped with the take...