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Associative Register Assignment Stack

IP.com Disclosure Number: IPCOM000044355D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 3 page(s) / 50K

Publishing Venue

IBM

Related People

Emma, PG: AUTHOR [+5]

Abstract

A relatively small Associative Register Assignment Stack (ARAS) can be used to verify entries in an Operand History Table (OHT) at I-fetch time. This would preclude superfluous cache-bus cycles, eliminate the need for an AGEN cycle, and reduce the bandwidth requirement on the register set. An ARAS is an LRU (least recently used) stack of entries, where each entry consists of the pair {Instruction Address, Name of Register used for AGEN}. Each instruction that has a memory source operand will make an entry in the table, e.g., if the instruction L R1,10(R2,0) is fetched from location 30, it will make the entry {30,2} in the ARAS since R2 is used to generate the source operand address. On subsequent fetches of this instruction, the instruction address (30) is used as an associative key on the ARAS.

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Associative Register Assignment Stack

A relatively small Associative Register Assignment Stack (ARAS) can be used to verify entries in an Operand History Table (OHT) at I-fetch time. This would preclude superfluous cache-bus cycles, eliminate the need for an AGEN cycle, and reduce the bandwidth requirement on the register set. An ARAS is an LRU (least recently used) stack of entries, where each entry consists of the pair {Instruction Address, Name of Register used for AGEN}. Each instruction that has a memory source operand will make an entry in the table, e.g., if the instruction L R1,10(R2,0) is fetched from location 30, it will make the entry {30,2} in the ARAS since R2 is used to generate the source operand address. On subsequent fetches of this instruction, the instruction address (30) is used as an associative key on the ARAS. If an entry {30,*} is found in the ARAS, then it is known that the register that is used to AGEN for the instruction (in this case, R2) has not been altered since the last time that this instruction was executed. Thus, the operand address that is contained in the Operand History Table (OHT) is the same address that an AGEN cycle on 10(R2,0) would produce. Hence, the operand can be fetched directly, and it is unnecessary to read R2 and perform an AGEN. Whenever a register sink is specified by an instruction, the register name is keyed to the R-field in the ARAS, and all entries that match this register name are deleted from the ARAS. For example, the entry {30,2} that was created by L R1,10(R2,0) would be deleted by an instruction LR R2,R5. Since instructions are decoded in order, this deletion can be performed during the decode cycle, i.e., the deletion can only impact subsequent instructions. Suppose that the ARAS contains the entry {30,2}, and the following subsequence occurs in the I-stream: Name Address Instruction A 2E LR

R2,R5 B 30 L R1,10(R2,0) It may be the case that B is fetched before A is decoded. Thus, the associative compare done on address 30 by instruction B would yield a match if the compare was performed at I-fetch time. This match would erroneously validate the operand address contained in the OHT. Thus, in order to insure that the OHT contains a valid entry, the associative compare must also be done when B is decoded (i.e., since A is decoded first, the entry {30,2} will have been deleted). In fact, a compare done at I-fetch time is optional, and it has only a minor benefit. The benefit is that if a non-match occurs, then operand prefetch can be given lower priority at the cache if other cache requests are pending. This will preclude a superfluous cache-bus cycle. An associative compare must be done on the ARAS during the decode cycle. A match will verify that the address in the OHT is valid. Since...