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Hardware That Simplifies the Testing Process by Making Chip and Module Test Compatible

IP.com Disclosure Number: IPCOM000044357D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 24K

Publishing Venue

IBM

Related People

Ostapko, DL: AUTHOR [+2]

Abstract

Making chip and module tests compatible simplifies the testing process and takes advantage of the test data computed at the chip level by applying them to the module level directly. To make a chip-in-place test possible, hardware can be added to each chip so that it becomes a natural testing entity by either latching all inputs 11 or all outputs 12. Latching all inputs 11 makes it possible to use the chip test data at the module level as well. Thus, any test pattern can be applied to a chip and the result of the test will either appear at a module output 12 or at a chip input 11 where it will be latched up, not only testing the chip but also the interconnections between chips. The module has two modes of operation: a normal mode 13=0 and a test mode 13=1.

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Hardware That Simplifies the Testing Process by Making Chip and Module Test Compatible

Making chip and module tests compatible simplifies the testing process and takes advantage of the test data computed at the chip level by applying them to the module level directly. To make a chip-in-place test possible, hardware can be added to each chip so that it becomes a natural testing entity by either latching all inputs 11 or all outputs 12. Latching all inputs 11 makes it possible to use the chip test data at the module level as well. Thus, any test pattern can be applied to a chip and the result of the test will either appear at a module output 12 or at a chip input 11 where it will be latched up, not only testing the chip but also the interconnections between chips. The module has two modes of operation: a normal mode 13=0 and a test mode 13=1. The objective of this procedure is to leave the module in its original functional configuration in normal mode and to allow for an efficient chip-in-place test in test mode. The test mode input 13 is common to all chip inputs. Whenever test mode 13 = 0, gates 14 and 15 are disabled, and there is a direct connection between input 11 and output 12 through gates 16 and 17; when test mode 13 = 1, gate 16 is disabled, allowing the latch 18 to reside between input 11 and output 12. The latch 18 serves two purposes in the test mode: chip-in-place test data can be supplied via the scan-in path 19 when a test is applied, and the test r...