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Parallel Signature Analysis Response Comparator

IP.com Disclosure Number: IPCOM000044358D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 3 page(s) / 64K

Publishing Venue

IBM

Related People

Hermann, AL: AUTHOR [+3]

Abstract

A parallel signature analysis response comparator determines, through data expansion, an exact faulty response from a parallel signature value in a three-level hierarchy memory by using a parallel signature analyzer and parallel memory devices instead of their serial counterparts. This provides a third hierarchy level of memory added for storing the grand total signature from the second hierarchy level of memory. This permits a geometric increase in data response storage for a linear increase in memory levels. Any product or device performing self-test can have multiple pins monitored simultaneously for a signature by a signature analysis response comparator (SARC).

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Parallel Signature Analysis Response Comparator

A parallel signature analysis response comparator determines, through data expansion, an exact faulty response from a parallel signature value in a three- level hierarchy memory by using a parallel signature analyzer and parallel memory devices instead of their serial counterparts. This provides a third hierarchy level of memory added for storing the grand total signature from the second hierarchy level of memory. This permits a geometric increase in data response storage for a linear increase in memory levels. Any product or device performing self-test can have multiple pins monitored simultaneously for a signature by a signature analysis response comparator (SARC). If 1K of random- access memory (RAM), the first hierarchy memory level, is used for storing the response data and a second hierarchy level of 1K RAM is used for storing 1,000 signatures, each signature value is equivalent to 1,000 cycles of compressed data, then 1,000,000 data responses have been stored for data expansion. The third level memory in hierarchy stores 1,000 signatures, with each signature value containing 1,000,000 cycles of compressed data. This added 1K of RAM gives the capacity to store one billion responses, any of which can be isolated as a fault. Self-test has to be invoked three times to allow the SARC to isolate the faulty response from the compressed data. Referring to the figure, the self-test based product sets the mask register 1a so that SARC will monitor those product pins corresponding to the mask bits containing a '1'. The mode register 1c is also set by the test-based product. A window bit 2, set to a '1', starts the SARC compressing the responses changing on the product pins. The compression cycle is synchronized by the product clock cycle. When the window bit 2 is set to a '0', SARC stops generating the signature. A second mode bit, test memory enable 3, enables the test response memory 4a and the test signature memory 5a and 6a to store 1,000 responses from the product pins and 1,000 signatures from the signature register 1b, respectively. While the product is performing self- test, memory 4a fills up with 1,000 responses and a signature for those patterns is stored from the signature register 1b into the first location in memory 5a addressed by the counter 7a. As self-test continues to run, counter 8a resets to memory 4a's first location and again fills with the next 1,000 responses. The signature for those responses is stored in the second location of memory 5a. The signature register 1b is never reset during a self-test run or during data compression 9. This process continues until the test signature memory 5a is filled with 1K signatures. The last 1K...