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Adaptive Test Timing Characterization

IP.com Disclosure Number: IPCOM000044360D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 3 page(s) / 49K

Publishing Venue

IBM

Related People

Young, DC: AUTHOR [+2]

Abstract

There are functional testers that do not have the capability to update pin timing (the DELAY parameter) according to the device-under-test's (DUT) measured signal transition. Such testers apply the tests (including the timing setup) in a fixed sequence and stop on failure. The following describes a test timing characterization concept, circuit, and test procedure that augments such functional testers with a program board circuit that, when inserted between the tester and the DUT pins, updates the DELAY timing on a per device tested basis without requiring tester hardware update. Tests that are used to tailor the pin timings to a DUT are called Timing Characterization Routines (TCRs). The TCRs apply only stimuli (no measures), because the tester "stops on first failure".

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Adaptive Test Timing Characterization

There are functional testers that do not have the capability to update pin timing (the DELAY parameter) according to the device-under-test's (DUT) measured signal transition. Such testers apply the tests (including the timing setup) in a fixed sequence and stop on failure. The following describes a test timing characterization concept, circuit, and test procedure that augments such functional testers with a program board circuit that, when inserted between the tester and the DUT pins, updates the DELAY timing on a per device tested basis without requiring tester hardware update. Tests that are used to tailor the pin timings to a DUT are called Timing Characterization Routines (TCRs). The TCRs apply only stimuli (no measures), because the tester "stops on first failure". The described concept requires that all TCRs, which have both stimuli and responses, be run prior to applying the functional test. Each TCR sets up the tester for a desired time slice and the adaptive test timing characterization (ATTC) hardware accumulates the TCR results which adjust the timing prior to applying the functional test. After the TCRs are run, the ATTC sets a delay deviation for the DUT. Each set of TCRs divides the tester cycle into n nanosecond time slices. TCR1 corresponds to the beginning of the "TCR sampling window". Each TCR applies an up pulse (e.g., 5 ns wide), which is used to AND with a primary output (PO) of the DUT. Thus, depending on whether the ANDed output is a pulse or a zero, ATTC can identify the PO's transition (within the window) by keeping track (in the COUNTER) of the number of pulses detected. The procedure for determining the up time of the PO begins with n-1=TCR sampling window/TCR pulse width. When (PO AND TCRi) = logic 1, then increment the COUNTER in the ATTC hardware by 1. The 'sampling window' is the time slot where a PO transition is expected. The sampling window must be less than the tester cycle. The ATTC circuit description is as follows: 1. RAM 11 (8 of 1 bit by lK static RAM) consists of a. Address bus 12 (10 bits), b. Data bus "RAM DATA 13" consisting of 8 bits or a number of bits required to set the PROG. DELAY 14, and c. RAM CNTL 15 which consists of 2 controls-CHIP SELECT & READ/WRITE, The RAM 11 is used to store the "delay" translation table. 2. The COUNTER 16 (10-bit wide) is incremented by an input rising edge. A positive transition on the 'ck' input increments COUNTER 16 by 1, and a pulse at the RESET 17 resets COUNTER 16 to 0. The tester increments COUNTER 16 by asserting a positive pulse on the ADDR PULSE 18; otherwise, ADDR PULSE stays low. 3. The OR gate 19 is used to increment COUNTER 16. It allows COUNTER 16 to be incremented from the tester (with ADDR PULSE 18) or from the DUT 20 pin. 4. The multiplexer (MUX) 21 determines whether the up or down level from DUT 20 will be used to increment C...