Browse Prior Art Database

Associative Clock Control for Signature Analysis

IP.com Disclosure Number: IPCOM000044362D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 68K

Publishing Venue

IBM

Related People

Young, DC: AUTHOR [+2]

Abstract

A self-stimulating Signature Analysis (SA) procedure is tailored to test and diagnose printed circuit boards (PCBs) which include functional elements, such as microprocessors and microprocessor-support devices. SA methodology compresses a string of response values (logic 1, 0) into a signature, a distinct 16-bit number usually written in hexadecimal form. SA requires that stimuli drive the device under test (DUT) and that the responses thereto be accumulated in the signature accumulator. The DUT's system clock, in general, controls when the response values are processed into the signature accumulator. The microprocessor op codes are such that some commands (op codes) have cycles that have "don't care" conditions. In the past, the op codes with "don't care" states were not included in the test program.

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Associative Clock Control for Signature Analysis

A self-stimulating Signature Analysis (SA) procedure is tailored to test and diagnose printed circuit boards (PCBs) which include functional elements, such as microprocessors and microprocessor-support devices. SA methodology compresses a string of response values (logic 1, 0) into a signature, a distinct 16- bit number usually written in hexadecimal form. SA requires that stimuli drive the device under test (DUT) and that the responses thereto be accumulated in the signature accumulator. The DUT's system clock, in general, controls when the response values are processed into the signature accumulator. The microprocessor op codes are such that some commands (op codes) have cycles that have "don't care" conditions. In the past, the op codes with "don't care" states were not included in the test program. The procedure described herein permits the execution of op codes having "don't care" conditions. It also bypasses some of the cycles within the command, rather than omitting the entire op code from the test program. At every occurrence of a stored op code, the circuit automatically bypasses the "don't care" cycles, i.e., prevents these cycles from being incorporated in the SA. The 5-to-32 decoder 11 (Fig. 1) generates two latch controls for each of the sixteen OP CODE RECOGNIZERS 12. The OP CODE RECOGNIZER 12 is used to store the op code with "don't care" condition and the number of "don't care" cycles to be ignored by the SA circuitry 13. During the test program execution, the OP CODE RECOGNIZER 12 recognizes the op code with "don't care" condition and blocks the number of clock signals sent to SA 13. During the test initialization phase (Fig. 2), latches A and B are loaded with the op code and the number of cycles to be ignored by SA 13. Once the test program is initiated, the OP COD...