Browse Prior Art Database

Implementing Instruction/Execution Cycle Overlap With an Opcode Branch CONTROL Storage in a Microcode-Controlled Sequential Computer

IP.com Disclosure Number: IPCOM000044366D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 66K

Publishing Venue

IBM

Related People

Chiu, PC: AUTHOR

Abstract

Improving system performance in a microcode-controlled sequential computer is accomplished by adding one opcode branch control storage 18 (OP-BR-CS) to the existing control storage 11 (CS) for implementing Instruction/Execution (I/E) cycle overlap operation, while the existing sequential I/E cycle microcode remains unchanged. The existing CS mechanism (Fig. 1) consists of CS 11 containing all processor microcode, the CS address register (CSAR) 12 for assembling the next microword address and control register (C-REG) 13 containing the microword to be executed by the processor. Under the existing CS mechanism and the sequential I/E cycle microcode, a microword is read from CS 11 and set in the C-REG buffer (CRB) 14 before it is set in the C-REG 13 at the end of the current machine cycle.

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Implementing Instruction/Execution Cycle Overlap With an Opcode Branch CONTROL Storage in a Microcode-Controlled Sequential Computer

Improving system performance in a microcode-controlled sequential computer is accomplished by adding one opcode branch control storage 18 (OP-BR-CS) to the existing control storage 11 (CS) for implementing Instruction/Execution (I/E) cycle overlap operation, while the existing sequential I/E cycle microcode remains unchanged. The existing CS mechanism (Fig. 1) consists of CS 11 containing all processor microcode, the CS address register (CSAR) 12 for assembling the next microword address and control register (C-REG) 13 containing the microword to be executed by the processor. Under the existing CS mechanism and the sequential I/E cycle microcode, a microword is read from CS 11 and set in the C-REG buffer (CRB) 14 before it is set in the C-REG 13 at the end of the current machine cycle. The I/E overlap control (I/E OVLP CONTROL) 15 decodes the microword in the CRB 14. If it is not the Instruction cycle (I- cycle) microword 'LOP' 19, then the microword in the CRB 14 is set in the C-REG
13. If, however, it is the I-cycle microword 'LOP' 16, the output of the CRB 14 is blocked and the C-REG 13 is set from the Opcode Branch Register (OBR) 20. The execution of the next instruction begins in subsequent machine cycles. The I-cycle unit 17, concurrent with the execution cycle (E-cycle) of the Nth instruction (In), performs the following func...