Browse Prior Art Database

Multiplexed Cpu-Based Store Protect Design

IP.com Disclosure Number: IPCOM000044368D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Boguski, MJ: AUTHOR [+4]

Abstract

A multiplexed central processing unit (CPU)-based store protect design (Fig. 1) allows storage protect hardware to be implemented on a CPU card whereby the protect hardware is shared by both the CPU and the I/O subsystem. This design facilitates using the system data bus of a dynamic random-access memory (DRAM) implemented memory system to transmit both storage data and storage protect information or keys. Placing the storage protect function on the CPU card frees up card I/O pins that would otherwise have to be used to transmit the key and key miss error signals 11. Having the storage protection hardware on the CPU card eliminates the need to duplicate the protection hardware on each memory card.

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Multiplexed Cpu-Based Store Protect Design

A multiplexed central processing unit (CPU)-based store protect design (Fig. 1) allows storage protect hardware to be implemented on a CPU card whereby the protect hardware is shared by both the CPU and the I/O subsystem. This design facilitates using the system data bus of a dynamic random-access memory (DRAM) implemented memory system to transmit both storage data and storage protect information or keys. Placing the storage protect function on the CPU card frees up card I/O pins that would otherwise have to be used to transmit the key and key miss error signals 11. Having the storage protection hardware on the CPU card eliminates the need to duplicate the protection hardware on each memory card. However, placing the storage protection function on the CPU card presents the problem of how to get the I/O key 12 to the key match hardware without using a special bus from the I/O to the CPU card. By multiplexing the I/O key 12 onto the system data bus 13, a dedicated key bus is not necessary. Because of the DRAM-type memory, the system data bus 13 is inactive during the early part of the memory access. This inactive period can be used to transfer the storage key to the CPU across the data bus 13, thus reducing the I/O pin count and simplifying storage design. The timing diagram (Fig. 2) shows the timing relationships for the address, data and control lines shown in Fig. 1. It can be seen that the fall of the I/O early column...