Browse Prior Art Database

Symmetrical Processor

IP.com Disclosure Number: IPCOM000044372D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 3 page(s) / 56K

Publishing Venue

IBM

Related People

Dutton, PF: AUTHOR [+2]

Abstract

A symmetrical processor (S/P) is implemented by designing a first processor with the proper control logic adding a second, identical processor and then integrating both of them together with two main memory units (basic storage module) (BSM)). Starting with a base system (Fig. 1) containing the 00 processor and a selection of BSM 00 sizes, a second processor, processor 01, is then added, significantly increasing performance, flexibility and availability. Processor 00 with BSM 00 is a standard uniprocessor (U/P). Adding processor 01 turns the system into an attached processor (A/P). If an A/P is designed to be symmetrical and a second BSM, BSM 01, is added, a symmetrical processor is created. A S/P can improve availability, increase performance and increase flexibility beyond that of an A/P.

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Symmetrical Processor

A symmetrical processor (S/P) is implemented by designing a first processor with the proper control logic adding a second, identical processor and then integrating both of them together with two main memory units (basic storage module) (BSM)). Starting with a base system (Fig. 1) containing the 00 processor and a selection of BSM 00 sizes, a second processor, processor 01, is then added, significantly increasing performance, flexibility and availability. Processor 00 with BSM 00 is a standard uniprocessor (U/P). Adding processor 01 turns the system into an attached processor (A/P). If an A/P is designed to be symmetrical and a second BSM, BSM 01, is added, a symmetrical processor is created. A S/P can improve availability, increase performance and increase flexibility beyond that of an A/P. Processor 00 with BSM 00 can be run as a U/P at the same time as processor 01, with BSM 01, is run as a U/P.

This configuration increases overall system performance and permits more channels to be configured. In effect, this is two U/P's in the same box which can be used completely independent of each other. The system can also be run as an A/P with BSM 00 as low memory and BSM 01 as high memory, or with BSM 01 as low memory and BSM 00 as high memory. This configuration permits an increased access to the BSM from the channels. Allowing faster access to the BSM permits more channels to be added to the system. The S/P can be arranged in a number of configurations for upgradability reasons, or due to some kind of a system failure. The following combinations are possible: a. Processor 00 and BSM 00 as a U/P or Processor 01 and BSM 01 as a U/P, b. Processor 00 and BSM 01 as a U/P or Processor 01 and BSM 00 as a U/P, c. Processor 00 and 01 with BSM 00 as an A/P or Processor 00 and 01 with BSM 01 as an A/P, and d. Processor 00 and 01 with BSM 00 and 01 as an A/P or two stand-alone U/P's.

Due to the symmetry of design, the components on one processor are identical to the components on the other processor. This reduces the overall number of system part numbers and thereby reduces the problems associated with having large quantities of different part numbers, field stocking, assembly lines, testing, etc. Data management for the two BSM A/P processor is controlled as follows (Fig. 2): BSM 00 will be assigned as low memory, and BSM 01 will be assigned as high memory. CACHE 00 and CACHE 01 can contain data from BSM 00 or 01. If processor 00 addresses a page of data, and the data is in CACHE 00, storage controls 00 will perform read or write. If processor 01 addresses a page of data, and the data is in CACHE 01, storage...