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Circuit for Measuring Pulse Periods and Pulse Lengths

IP.com Disclosure Number: IPCOM000044374D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 3 page(s) / 29K

Publishing Venue

IBM

Related People

Arendt, K: AUTHOR [+2]

Abstract

The illustrated circuit permits measuring deviations from nominal pulse period or pulse length values with high accuracy and resolution. During measuring, clock pulses are counted, and a first counter CTR1, used for that purpose, stores a number of pulses amounting to half its capacity C. A second counter CTR2 serves to count the wrap- around events of CTR1. The permissible pulse deviations are chosen to correspond to C/2, so that variations of + C/2 may be measured by the circuit. To cope with different pulse periods and pulse lengths, CTR1 is preset to a suitable value, and overflow pulses to be counted by CTR2 are derived from a suitable stage of CTR1. In the illustrated circuit, pulses are applied to an input stage INP supplying the appropriate start/stop counting signals S/S to a timing circuit TCT.

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Circuit for Measuring Pulse Periods and Pulse Lengths

The illustrated circuit permits measuring deviations from nominal pulse period or pulse length values with high accuracy and resolution. During measuring, clock pulses are counted, and a first counter CTR1, used for that purpose, stores a number of pulses amounting to half its capacity C. A second counter CTR2 serves to count the wrap- around events of CTR1. The permissible pulse deviations are chosen to correspond to C/2, so that variations of + C/2 may be measured by the circuit. To cope with different pulse periods and pulse lengths, CTR1 is preset to a suitable value, and overflow pulses to be counted by CTR2 are derived from a suitable stage of CTR1. In the illustrated circuit, pulses are applied to an input stage INP supplying the appropriate start/stop counting signals S/S to a timing circuit TCT. The pulse periods to be measured may optionally start or end at the positive or negative pulse edges or they may start at an edge going in one direction and end at the next edge going in the other direction. INP generates the necessary signals S/S. TCT includes a clock of 25 MHz and supplies timing control signals CTRL to the illustrated units. CTR1 may be preset to a value P by circuit PS1. At the end of the measuring period, the contents of CTR1 are transferred to an output register REG by a connection switch CS1. Switch CS1 also selects the appropriate most significant stage of CTR1 from which wrap-around pulses are derived as counting pulses CT for CTR2. In a practical embodiment, a 16-stage counter is used for CRT1, with the clock pulses being applied to its first stage. If 10 out of the 16 stages of CTR1 (having a capacity C and a maximum count of 1024, so that C/2 = 512) and a clock frequency of 25 MHz amounting to a clock pulse period of 40 ns are used, the minimum deviation that can be measured is + 512 x 40 ns = + 20.48 ms. Using those ten highest stages of CTR1, the maximum value that can be measured is + 40 x 26 x 512 ns = 1_310.72 ms. Generally, depending on the least significant bit posit...